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SN74LS197D PDF预览

SN74LS197D

更新时间: 2024-11-11 23:06:19
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 计数器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 229K
描述
4-STAGE PRESETTABLE RIPPLE COUNTERS

SN74LS197D 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:SOP, SOP14,.25Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.81
其他特性:DIVIDE BY 2 AND DIVIDE BY 8 FUNCTIONS计数方向:UP
系列:LSJESD-30 代码:R-PDSO-G14
JESD-609代码:e0长度:8.65 mm
负载电容(CL):15 pF负载/预设输入:YES
逻辑集成电路类型:BINARY COUNTER最大频率@ Nom-Sup:30000000 Hz
最大I(ol):0.008 A工作模式:ASYNCHRONOUS
位数:3功能数量:2
端子数量:14最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):27 mA传播延迟(tpd):95 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Counters最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:NEGATIVE EDGE宽度:3.9 mm
最小 fmax:30 MHzBase Number Matches:1

SN74LS197D 数据手册

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SN54/74LS196  
SN54/74LS197  
4-STAGE PRESETTABLE  
RIPPLE COUNTERS  
TheSN54/74LS196decadecounterispartitionedintodivide-by-twoanddi-  
vide-by-five sections which can be combined to count either in BCD (8, 4, 2, 1)  
sequence or in a bi-quinary mode producing a 50% duty cycle output. The  
SN54/74LS197 contains divide-by-two and divide-by-eight sections which  
can be combined to form a modulo-16 binary counter. Low Power Schottky  
technology is used to achieve typical count rates of 70 MHz and power dis-  
sipation of only 80 mW.  
4-STAGE PRESETTABLE  
RIPPLE COUNTERS  
LOW POWER SCHOTTKY  
Both circuit types have a Master Reset (MR) input which overrides all other  
inputs and asynchronously forces all outputs LOW. A Parallel Load input (PL)  
overrides clocked operations and asynchronously loads the data on the Par-  
allel Data inputs (P ) into the flip-flops. This preset feature makes the circuits  
n
J SUFFIX  
CERAMIC  
CASE 632-08  
usable as programmable counters. The circuits can also be used as 4-bit  
latches, loading data from the Parallel Data inputs when PL is LOW and stor-  
ing the data when PL is HIGH.  
14  
1
Low Power Consumption — Typically 80 mW  
High Counting Rates — Typically 70 MHz  
Choice of Counting Modes — BCD, Bi-Quinary, Binary  
Asynchronous Presettable  
Asynchronous Master Reset  
Easy Multistage Cascading  
N SUFFIX  
PLASTIC  
CASE 646-06  
14  
Input Clamp Diodes Limit High Speed Termination Effects  
1
CONNECTION DIAGRAM DIP (TOP VIEW)  
D SUFFIX  
SOIC  
CASE 751A-02  
14  
1
NOTE:  
The Flatpak version  
has the same pinouts  
(Connection Diagram) as  
the Dual In-Line Package.  
ORDERING INFORMATION  
SN54LSXXXJ  
Ceramic  
SN74LSXXXN Plastic  
SN74LSXXXD SOIC  
PIN NAMES  
LOADING (Note a)  
LOGIC SYMBOL  
HIGH  
LOW  
1.5 U.L.  
CP  
Clock (Active LOW Going Edge)  
Input to Divide-by-Two Section  
Clock (Active LOW Going Edge)  
Input to Divide-by-Five Section  
Clock (Active LOW Going Edge)  
Input to Divide-by-Eight Section  
Master Reset (Active LOW) Input  
Parallel Load (Active LOW) Input  
Data Inputs  
1.0 U.L.  
0
CP (LS196)  
2.0 U.L.  
1.0 U.L.  
1.75 U.L.  
0.8 U.L.  
1
CP (LS197)  
1
MR  
PL  
1.0 U.L.  
0.5 U.L.  
0.5 U.L.  
10 U.L.  
0.5 U.L.  
0.25 U.L.  
P –P  
0
0.25 U.L.  
3
Q –Q  
Outputs (Notes b, c)  
5 (2.5) U.L.  
0
3
NOTES:  
a. 1 TTL Unit Load (U.L.) = 40µA HIGH/1.6 mA LOW.  
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)  
b. Temperature Ranges.  
c. In addition to loading shown, Q can also drive CP .  
0
1
FAST AND LS TTL DATA  
5-372  

SN74LS197D 替代型号

型号 品牌 替代类型 描述 数据表
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