5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 计数器> SN74LS197NDS
SN74LS197NDS PDF预览

SN74LS197NDS

更新时间： 2024-11-12 13:13:51
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 计数器
页数 文件大小 规格书
6页 93K
描述
LS SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP BINARY COUNTER, PDIP14, PLASTIC, DIP-14

阅读下载

中文翻译

获取价格

SN74LS197NDS 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：DIP, DIP14,.3
针数：14Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.74
计数方向：UP系列：LS
JESD-30 代码：R-PDIP-T14JESD-609代码：e0
长度：18.86 mm负载/预设输入：YES
逻辑集成电路类型：BINARY COUNTER工作模式：ASYNCHRONOUS
位数：3功能数量：2
端子数量：14最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP14,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
传播延迟（tpd）：95 ns认证状态：Not Qualified
座面最大高度：5.08 mm子类别：Counters
最大供电电压 (Vsup)：5.25 V最小供电电压 (Vsup)：4.75 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：TTL温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：NEGATIVE EDGE
宽度：7.62 mm最小 fmax：30 MHz
Base Number Matches：1

SN74LS197NDS 数据手册

 浏览型号SN74LS197NDS的Datasheet PDF文件第2页浏览型号SN74LS197NDS的Datasheet PDF文件第3页浏览型号SN74LS197NDS的Datasheet PDF文件第4页浏览型号SN74LS197NDS的Datasheet PDF文件第5页浏览型号SN74LS197NDS的Datasheet PDF文件第6页 
SN54/74LS196  
SN54/74LS197  
4-STAGE PRESETTABLE  
RIPPLE COUNTERS  
TheSN54/74LS196decadecounterispartitionedintodivide-by-twoanddi-  
vide-by-five sections which can be combined to count either in BCD (8, 4, 2, 1)  
sequence or in a bi-quinary mode producing a 50% duty cycle output. The  
SN54/74LS197 contains divide-by-two and divide-by-eight sections which  
can be combined to form a modulo-16 binary counter. Low Power Schottky  
technology is used to achieve typical count rates of 70 MHz and power dis-  
sipation of only 80 mW.  
4-STAGE PRESETTABLE  
RIPPLE COUNTERS  
LOW POWER SCHOTTKY  
Both circuit types have a Master Reset (MR) input which overrides all other  
inputs and asynchronously forces all outputs LOW. A Parallel Load input (PL)  
overrides clocked operations and asynchronously loads the data on the Par-  
allel Data inputs (P ) into the flip-flops. This preset feature makes the circuits  
n
J SUFFIX  
CERAMIC  
CASE 632-08  
usable as programmable counters. The circuits can also be used as 4-bit  
latches, loading data from the Parallel Data inputs when PL is LOW and stor-  
ing the data when PL is HIGH.  
14  
1
• Low Power Consumption — Typically 80 mW  
• High Counting Rates — Typically 70 MHz  
• Choice of Counting Modes — BCD, Bi-Quinary, Binary  
• Asynchronous Presettable  
• Asynchronous Master Reset  
• Easy Multistage Cascading  
N SUFFIX  
PLASTIC  
CASE 646-06  
14  
• Input Clamp Diodes Limit High Speed Termination Effects  
1
CONNECTION DIAGRAM DIP (TOP VIEW)  
V
MR  
13  
Q
P
P
Q
CP  
D SUFFIX  
SOIC  
CASE 751A-02  
CC  
3
3
1
1
0
14  
12  
11  
10  
9
8
14  
1
NOTE:  
The Flatpak version  
has the same pinouts  
(Connection Diagram) as  
the Dual In-Line Package.  
ORDERING INFORMATION  
SN54LSXXXJ  
Ceramic  
SN74LSXXXN Plastic  
SN74LSXXXD SOIC  
1
2
3
4
5
6
7
PL  
Q
P
P
Q
CP  
1
GND  
2
2
0
0
PIN NAMES  
LOADING (Note a)  
LOGIC SYMBOL  
HIGH  
LOW  
1.5 U.L.  
1
4
10 3 11  
CP  
Clock (Active LOW Going Edge)  
Input to Divide-by-Two Section  
Clock (Active LOW Going Edge)  
Input to Divide-by-Five Section  
Clock (Active LOW Going Edge)  
Input to Divide-by-Eight Section  
Master Reset (Active LOW) Input  
Parallel Load (Active LOW) Input  
Data Inputs  
1.0 U.L.  
0
PL  
P
P P P  
0 1 2 3  
8
6
CP  
CP  
0
CP (LS196)  
1
2.0 U.L.  
1.0 U.L.  
1.75 U.L.  
0.8 U.L.  
1
MR  
Q
Q Q Q  
0 1 2 3  
CP (LS197)  
1
MR  
PL  
1.0 U.L.  
0.5 U.L.  
0.5 U.L.  
10 U.L.  
0.5 U.L.  
0.25 U.L.  
13  
V
5
9
2 12  
= PIN 14  
CC  
P –P  
0
0.25 U.L.  
3
GND = PIN 7  
Q –Q  
Outputs (Notes b, c)  
5 (2.5) U.L.  
0
3
NOTES:  
a. 1 TTL Unit Load (U.L.) = 40µA HIGH/1.6 mA LOW.  
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)  
b. Temperature Ranges.  
c. In addition to loading shown, Q can also drive CP .  
0
1
FAST AND LS TTL DATA  
5-1  
123456

中文翻译

下载PDF

与SN74LS197NDS相关器件

型号 品牌 获取价格 描述 数据表
SN74LS197NP1 TI

获取价格

 		IC,COUNTER,UP,4-BIT BINARY,LS-TTL,DIP,14PIN,PLASTIC
SN74LS197NS MOTOROLA

获取价格

 		LS SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, PDIP14, PLASTIC, DIP-14
SN74LS19A TI

获取价格

 		SCHMITT-TRIGGER POSITIVE-NAND GATES AND INVERTERS WITH TOTEM-POLE OUTPUTS
SN74LS19AD TI

获取价格

 		SCHMITT-TRIGGER POSITIVE-NAND GATES AND INVERTERS WITH TOTEM-POLE OUTPUTS
SN74LS19ADE4 TI

获取价格

 		LS SERIES, HEX 1-INPUT INVERT GATE, PDSO14, GREEN, PLASTIC, MS-012AB, SOIC-14
SN74LS19ADG4 TI

获取价格

 		LS SERIES, HEX 1-INPUT INVERT GATE, PDSO14, GREEN, PLASTIC, MS-012AB, SOIC-14
SN74LS19ADR TI

获取价格

 		Hex Schmitt-Trigger Inverters 14-SOIC 0 to 70
SN74LS19ADRE4 TI

获取价格

 		Hex Schmitt-Trigger Inverters 14-SOIC 0 to 70
SN74LS19AJ TI

获取价格

 		SCHMITT-TRIGGER POSITIVE-NAND GATES AND INVERTERS WITH TOTEM-POLE OUTPUTS
SN74LS19AN TI

获取价格

 		SCHMITT-TRIGGER POSITIVE-NAND GATES AND INVERTERS WITH TOTEM-POLE OUTPUTS

与SN74LS197NDS相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证