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SN74LS173ANS PDF预览

SN74LS173ANS

更新时间: 2024-09-15 13:13:51
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 输出元件
页数 文件大小 规格书
6页 210K
描述
LS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP16, PLASTIC, DIP-16

SN74LS173ANS 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.33
其他特性:WITH HOLD MODE系列:LS
JESD-30 代码:R-PDIP-T16JESD-609代码:e0
长度:20.07 mm逻辑集成电路类型:D FLIP-FLOP
最大I(ol):0.024 A位数:4
功能数量:1端子数量:16
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V传播延迟(tpd):30 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:FF/Latches最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.62 mm
最小 fmax:50 MHzBase Number Matches:1

SN74LS173ANS 数据手册

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SN54/74LS173A  
4-BIT D-TYPE REGISTER  
WITH 3-STATE OUTPUTS  
The SN54/74LS173A is a high-speed 4-Bit Register featuring 3-state  
outputs for use in bus-organized systems. The clock is fully edge-triggered  
allowing either a load from the D inputs or a hold (retain register contents)  
4-BIT D-TYPE REGISTER  
WITH 3-STATE OUTPUTS  
depending on the state of the Input Enable Lines (IE , IE ). A HIGH on either  
1
2
Output Enable line (OE , OE ) brings the output to a high impedance state  
1
2
LOW POWER SCHOTTKY  
without affecting the actual register contents. A HIGH on the Master Reset  
(MR) input resets the Register regardless of the state of the Clock (CP), the  
Output Enable (OE , OE ) or the Input Enable (IE , IE ) lines.  
1
Fully Edge-Triggered  
3-State Outputs  
2
1
2
J SUFFIX  
CERAMIC  
CASE 620-09  
Gated Input and Output Enables  
Input Clamp Diodes Limit High-Speed Termination Effects  
16  
1
CONNECTION DIAGRAM DIP (TOP VIEW)  
N SUFFIX  
PLASTIC  
CASE 648-08  
16  
1
NOTE:  
The Flatpak version  
has the same pinouts  
(Connection Diagram) as  
the Dual In-Line Package.  
D SUFFIX  
SOIC  
CASE 751B-03  
16  
1
ORDERING INFORMATION  
SN54LSXXXJ  
Ceramic  
SN74LSXXXN Plastic  
SN74LSXXXD SOIC  
PIN NAMES  
LOADING (Note a)  
HIGH  
LOW  
D D  
Data Inputs  
0.5 U.L.  
0.25 U.L.  
0.25 U.L.  
0.25 U.L.  
0.25 U.L.  
LOGIC SYMBOL  
0
3
2
IE IE  
Input Enable (Active LOW)  
Output Enable (Active LOW) Inputs  
Clock Pulse (Active HIGH Going Edge)  
Input  
0.5 U.L.  
0.5 U.L.  
0.5 U.L.  
1
OE OE  
1
2
CP  
MR  
Q Q  
0
Master Reset Input (Active HIGH)  
Outputs (Note b)  
0.5 U.L.  
65 (25) U.L. 15 (7.5) U.L.  
0.25 U.L.  
3
NOTES:  
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.  
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)  
b. Temperature Ranges.  
FAST AND LS TTL DATA  
5-316  

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