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SN74HSTL16918DGG PDF预览

SN74HSTL16918DGG

更新时间： 2024-11-02 22:24:31
品牌 Logo 应用领域
德州仪器 - TI 存储触发器锁存器逻辑集成电路光电二极管双倍数据速率
页数 文件大小 规格书
5页 77K
描述
9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH

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SN74HSTL16918DGG 技术参数

生命周期：Obsolete包装说明：TSSOP,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.73Is Samacsys：N
系列：HST/TJESD-30 代码：R-PDSO-G48
长度：12.5 mm逻辑集成电路类型：D LATCH
位数：2功能数量：1
端子数量：48最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟（tpd）：5.2 ns
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.45 V最小供电电压 (Vsup)：3.15 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL触发器类型：POSITIVE EDGE
宽度：6.1 mmBase Number Matches：1

SN74HSTL16918DGG 数据手册

 浏览型号SN74HSTL16918DGG的Datasheet PDF文件第2页浏览型号SN74HSTL16918DGG的Datasheet PDF文件第3页浏览型号SN74HSTL16918DGG的Datasheet PDF文件第4页浏览型号SN74HSTL16918DGG的Datasheet PDF文件第5页 
SN74HSTL16918  
9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH  
SCES096C – APRIL 1997 – REVISED JANUARY 1999  
DGG PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
Inputs Meet JEDEC HSTL Std JESD 8-6 and  
Outputs Meet Level III Specifications  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
2Q1  
1Q1  
GND  
D1  
V
V
CC  
CC  
2
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
3
1Q2  
2Q2  
GND  
1Q3  
2Q3  
4
5
D2  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
6
V
CC  
D3  
7
Packaged in Plastic Thin Shrink  
Small-Outline Package  
8
D4  
GND  
1LE  
V
CC  
9
1Q4  
2Q4  
GND  
1Q5  
2Q5  
GND  
1Q6  
2Q6  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
description  
GND  
V
REF  
This 9-bit to 18-bit D-type latch is designed for  
3.15-V to 3.45-V V operation. The D inputs  
GND  
CC  
2LE  
GND  
D5  
D6  
D7  
accept HSTL levels and the Q outputs provide  
LVTTL levels.  
The SN74HSTL16918 is particularly suitable for  
driving an address bus to two banks of memory.  
Each bank of nine outputs is controlled with its  
own latch-enable (LE) input.  
V
CC  
1Q7  
2Q7  
GND  
1Q8  
2Q8  
V
CC  
D8  
D9  
Eachof the nine D inputs is tied to the inputs of two  
D-type latches that provide true data (Q) at the  
outputs. While LE is low, the Q outputs of the  
corresponding nine latches follow the D inputs.  
When LE is taken high, the Q outputs are latched  
at the levels set up at the D inputs.  
GND  
2Q9  
1Q9  
V
V
CC  
CC  
The SN74HSTL16918 is characterized for  
operation from 0°C to 70°C.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Q
LE  
D
H
L
L
L
H
L
†
Q
0
H
X
†
Output level before the  
indicated steady-state input  
conditions were established  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345

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SN74HSTL16918DGG 替代型号

型号 品牌 替代类型 描述 数据表
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