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SN74HSTL16919

更新时间： 2024-11-03 04:01:07
品牌 Logo 应用领域
德州仪器 - TI 存储锁存器输入元件双倍数据速率
页数 文件大小 规格书
8页 125K
描述
9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH WITH INPUT PULLUP RESISTORS

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SN74HSTL16919 数据手册

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SN74HSTL16919  
9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH  
WITH INPUT PULLUP RESISTORS  
SCES348 – MARCH 2001  
DGG PACKAGE  
(TOP VIEW)  
Member of Texas Instruments’ Widebus  
Family  
Inputs Meet JEDEC HSTL Std JESD 8-6,  
and Outputs Meet Level III Specifications  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
2Q1  
1Q1  
GND  
D1  
V
V
CC  
CC  
2
10-kΩ Pullup Resistor on Data and LE  
Inputs  
3
1Q2  
2Q2  
GND  
1Q3  
2Q3  
4
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
5
D2  
6
V
CC  
D3  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
7
8
D4  
GND  
1LE  
V
CC  
9
1Q4  
2Q4  
GND  
1Q5  
2Q5  
GND  
1Q6  
2Q6  
– 1000-V Charged-Device Model (C101)  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
GND  
description  
V
REF  
GND  
This 9-bit to 18-bit D-type latch is designed for  
3.15-V to 3.45-V V operation. The D inputs  
2LE  
GND  
D5  
D6  
D7  
CC  
accept HSTL levels and the Q outputs provide  
LVTTL levels.  
V
CC  
The SN74HSTL16919 is particularly suitable for  
driving an address bus to two banks of memory.  
Each bank of nine outputs is controlled with its  
own latch-enable (LE) input.  
1Q7  
2Q7  
GND  
1Q8  
2Q8  
V
CC  
D8  
D9  
GND  
2Q9  
1Q9  
Eachof the nine D inputs is tied to the inputs of two  
D-type latches that provide true data (Q) at the  
outputs. While LE is low, the Q outputs of the  
corresponding nine latches follow the D inputs.  
When LE is taken high, the Q outputs are latched  
at the levels set up at the D inputs.  
V
V
CC  
CC  
To ensure low I  
to ensure a differential voltage relative to V  
during power up or power down, 10-kΩ pullup resistors are included on the D and LE inputs  
CC  
. V  
must be applied prior to or at the same time as V , or  
REF REF CC  
V
must be pulled down to ground.  
REF  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
T
A
PACKAGE  
0°C to 70°C  
TSSOP – DGG Tape and reel  
SN74HSTL16919DGGR  
HSTL16919  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
Copyright 2001, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

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