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SN74HCT273NSRE4 PDF预览

SN74HCT273NSRE4

更新时间: 2024-11-06 12:15:03
品牌 Logo 应用领域
德州仪器 - TI 触发器
页数 文件大小 规格书
17页 776K
描述
OCTAL D-TYPE FLIP-FLOPS WITH CLEAR

SN74HCT273NSRE4 数据手册

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ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢊ ꢀꢁ ꢈꢃ ꢄꢅ ꢆꢇ ꢈꢉ  
ꢋ ꢅꢆꢌꢍ ꢎꢏꢆ ꢐꢑ ꢒ ꢓ ꢍ ꢔꢑ ꢏ ꢓꢍꢋ ꢑ ꢀ  
ꢕ ꢔꢆꢄ ꢅ ꢍꢒ ꢌꢖ  
SCLS068E − NOVEMBER 1988 − REVISED AUGUST 2003  
D
D
D
D
D
D
Operating Voltage Range of 4.5 V to 5.5 V  
Outputs Can Drive Up To 10 LSTTL Loads  
D
D
D
D
Inputs Are TTL-Voltage Compatible  
Contain Eight D-Type Flip-Flops  
Direct Clear Input  
Low Power Consumption, 80-µA Max I  
CC  
Typical t = 12 ns  
pd  
4-mA Output Drive at 5 V  
Applications Include:  
− Buffer/Storage Registers  
− Shift Registers  
Low Input Current of 1 µA Max  
− Pattern Generators  
SN54HCT273 . . . J OR W PACKAGE  
SN74HCT273 . . . DB, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
SN54HCT273 . . . FK PACKAGE  
(TOP VIEW)  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
CLR  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
CLK  
3
2
1
20 19  
18  
4
5
6
7
8
2D  
2Q  
3Q  
3D  
4D  
8D  
7D  
7Q  
6Q  
6D  
17  
16  
15  
14  
9 10 11 12 13  
GND  
description/ordering information  
These devices are positive-edge-triggered D-type flip-flops with a common enable input. The ’HCT273 devices  
are similar to the ’HCT377 devices, but feature a common clear enable (CLR) input instead of a latched clock.  
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the  
positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not  
directly related to the positive-going pulse. When CLK is at either the high or low level, the D input has no effect  
at the output. The circuits are designed to prevent false clocking by transitions at CLR.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP − N  
Tube of 20  
Tube of 25  
Reel of 2000  
Reel of 2000  
Reel of 2000  
Tube of 70  
Reel of 2000  
Reel of 250  
Tube of 20  
Tube of 85  
Tube of 55  
SN74HCT273N  
SN74HCT273N  
SN74HCT273DW  
SN74HCT273DWR  
SN74HCT273NSR  
SN74HCT273DBR  
SN74HCT273PW  
SN74HCT273PWR  
SN74HCT273PWT  
SNJ54HCT273J  
SOIC − DW  
HCT273  
SOP − NS  
HCT273  
HT273  
−40°C to 85°C  
SSOP − DB  
TSSOP − PW  
HT273  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54HCT273J  
SNJ54HCT273W  
SNJ54HCT273FK  
SNJ54HCT273W  
SNJ54HCT273FK  
−55°C to 125°C  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢗ ꢁ ꢍꢒꢀꢀ ꢋ ꢆꢄ ꢒꢖꢕ ꢔꢀ ꢒ ꢁ ꢋꢆꢒꢎ ꢘꢙ ꢚꢛ ꢜꢝꢞ ꢟꢠꢡ ꢢꢘ ꢞꢝ ꢢꢘꢣ ꢚꢢꢛ ꢑꢖ ꢋ ꢎ ꢗ ꢅꢆ ꢔꢋ ꢁ  
ꢦꢣ ꢥ ꢣ ꢠ ꢡ ꢘ ꢡ ꢥ ꢛ ꢩ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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