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SN74HC682J PDF预览

SN74HC682J

更新时间: 2024-09-19 13:00:23
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
11页 417K
描述
IC,MAGNITUDE COMPARATOR,HC-CMOS,DIP,20PIN,CERAMIC

SN74HC682J 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:DIP, DIP20,.3Reach Compliance Code:not_compliant
风险等级:5.92Is Samacsys:N
JESD-30 代码:R-XDIP-T20逻辑集成电路类型:MAGNITUDE COMPARATOR
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:CERAMIC
封装代码:DIP封装等效代码:DIP20,.3
封装形状:RECTANGULAR封装形式:IN-LINE
电源:2/6 V认证状态:Not Qualified
子类别:Arithmetic Circuits表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUALBase Number Matches:1

SN74HC682J 数据手册

 浏览型号SN74HC682J的Datasheet PDF文件第2页浏览型号SN74HC682J的Datasheet PDF文件第3页浏览型号SN74HC682J的Datasheet PDF文件第4页浏览型号SN74HC682J的Datasheet PDF文件第5页浏览型号SN74HC682J的Datasheet PDF文件第6页浏览型号SN74HC682J的Datasheet PDF文件第7页 
SN54HC682, SN74HC682  
8-BIT MAGNITUDE COMPARATORS  
SCLS018D – MARCH 1984 – REVISED MARCH 2003  
Wide Operating Voltage Range of 2 V to 6 V  
±4-mA Output Drive at 5 V  
High-Current Outputs Drive Up To 10  
LSTTL Loads  
Compare Two 8-Bit Words  
100-kPullup Resistors Are on the  
Typical t = 22 ns  
Q Inputs  
pd  
SN54HC682 . . . J OR W PACKAGE  
SN74HC682 . . . DW OR N PACKAGE  
(TOP VIEW)  
SN54HC682 . . . FK PACKAGE  
(TOP VIEW)  
P > Q  
P0  
V
CC  
P = Q  
Q7  
1
2
3
4
5
6
7
8
9
20  
19  
18  
3
2
1
20 19  
18  
Q0  
P1  
Q7  
P7  
Q6  
P1  
Q1  
P2  
Q2  
P3  
4
5
6
7
8
17 P7  
16 Q6  
15 P6  
14 Q5  
13 P5  
12 Q4  
11 P4  
17  
16  
Q1  
P2  
15 P6  
14  
9 10 11 12 13  
Q2  
P3  
Q5  
Q3  
GND 10  
description/ordering information  
These magnitude comparators perform comparisons of two 8-bit binary or BCD words. The ’HC682 devices  
feature 100-kpullup termination resistors on the Q inputs for analog or switch data.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP – N  
Tube  
SN74HC682N  
SN74HC682N  
–40°C to 85°C  
–55°C to 125°C  
Tube  
SN74HC682DW  
SN74HC682DWR  
SNJ54HC682J  
SNJ54HC682W  
SNJ54HC682FK  
SOIC – DW  
HC682  
Tape and reel  
Tube  
CDIP – J  
CFP – W  
LCCC – FK  
SNJ54HC682J  
SNJ54HC682W  
SNJ54HC682FK  
Tube  
Tube  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
FUNCTION TABLE  
DATA  
INPUTS  
P, Q  
OUTPUTS  
P = Q P > Q  
P = Q  
P > Q  
P < Q  
L
H
H
H
L
H
The P < Q function can be  
generated by applying P = Q  
and P > Q to a 2-input NAND  
gate.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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