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SN74HC259PW PDF预览

SN74HC259PW

更新时间： 2024-09-07 22:17:47
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路光电二极管双倍数据速率
页数 文件大小 规格书
9页 137K
描述
8-BIT ADDRESSABLE LATCHES

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SN74HC259PW 技术参数

生命周期：ObsoleteReach Compliance Code：unknown
风险等级：5.83Is Samacsys：N
JESD-30 代码：R-PDSO-G16负载电容（CL）：50 pF
逻辑集成电路类型：D LATCH最大I（ol）：0.004 A
位数：8功能数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源：2/6 VProp。Delay @ Nom-Sup：33 ns
认证状态：Not Qualified子类别：FF/Latches
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
Base Number Matches：1

SN74HC259PW 数据手册

 浏览型号SN74HC259PW的Datasheet PDF文件第2页浏览型号SN74HC259PW的Datasheet PDF文件第3页浏览型号SN74HC259PW的Datasheet PDF文件第4页浏览型号SN74HC259PW的Datasheet PDF文件第5页浏览型号SN74HC259PW的Datasheet PDF文件第6页浏览型号SN74HC259PW的Datasheet PDF文件第7页 
SN54HC259, SN74HC259  
8-BIT ADDRESSABLE LATCHES  
SCLS134B – DECEMBER 1982 – REVISED MAY 1997  
SN54HC259 . . . J OR W PACKAGE  
SN74HC259 . . . D, N, OR PW PACKAGE  
(TOP VIEW)  
8-Bit Parallel-Out Storage Register  
Performs Serial-to-Parallel Conversion With  
Storage  
Asynchronous Parallel Clear  
Active-High Decoder  
S0  
S1  
S2  
Q0  
Q1  
Q2  
Q3  
GND  
V
CC  
CLR  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Enable Input Simplifies Expansion  
Expandable for n-Bit Applications  
Four Distinct Functional Modes  
G
D
Q7  
Q6  
Q5  
Q4  
Package Options Include Plastic  
Small-Outline (D), Thin Shrink  
Small-Outline (PW), and Ceramic Flat (W)  
Packages, Ceramic Chip Carriers (FK), and  
Standard Plastic (N) and Ceramic (J)  
300-mil DIPs  
SN54HC259 . . . FK PACKAGE  
(TOP VIEW)  
description  
These 8-bit addressable latches are designed for  
general-purpose storage applications in digital  
systems. Specific uses include working registers,  
serial-holding registers, and active-high decoders  
or demultiplexers. They are multifunctional  
devices capable of storing single-line data in eight  
addressable latches, and being a 1-of-8 decoder  
or demultiplexer with active-high outputs.  
3
2
1
20 19  
18  
S2  
Q0  
NC  
Q1  
Q2  
G
4
5
6
7
8
17  
16  
15  
14  
D
NC  
Q7  
Q6  
9 10 11 12 13  
Four distinct modes of operation are selectable by  
controlling the clear (CLR) and enable (G) inputs.  
In the addressable-latch mode, data at the data-in  
terminal is written into the addressed latch. The  
addressed latch follows the data input with all  
unaddressed latches remaining in their previous  
states. In the memory mode, all latches remain in  
their previous states and are unaffected by the  
data or address inputs. To eliminate the possibility  
of entering erroneous data in the latches, G  
should be held high (inactive) while the address  
lines are changing. In the 1-of-8 decoding or  
demultiplexing mode, the addressed output  
follows the level of the D input with all other  
outputs low. In the clear mode, all outputs are low  
and unaffected by the address and data inputs.  
NC – No internal connection  
The SN54HC259 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74HC259 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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