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SN74CB3Q3257 PDF预览

SN74CB3Q3257

更新时间: 2024-11-30 23:03:11
品牌 Logo 应用领域
德州仪器 - TI 解复用器
页数 文件大小 规格书
13页 334K
描述
4 BIT 1 OF 2 FET MULTIPLEXER/ DEMULTIPLEXER

SN74CB3Q3257 数据手册

 浏览型号SN74CB3Q3257的Datasheet PDF文件第2页浏览型号SN74CB3Q3257的Datasheet PDF文件第3页浏览型号SN74CB3Q3257的Datasheet PDF文件第4页浏览型号SN74CB3Q3257的Datasheet PDF文件第5页浏览型号SN74CB3Q3257的Datasheet PDF文件第6页浏览型号SN74CB3Q3257的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢆ ꢈꢉꢂ  
ꢃ ꢊꢅꢋ ꢌ ꢍ ꢊꢎ ꢏꢊ ꢈ ꢏ ꢐꢌ ꢑ ꢒꢓꢌ ꢋꢔ ꢓꢐ ꢕꢐꢖꢗ ꢘꢐꢑ ꢒꢓꢌꢋ ꢔ ꢓꢐ ꢕꢐ ꢖ  
ꢈ ꢙ ꢉ ꢊꢚ ꢗꢆ ꢙꢆ ꢊꢚ ꢓ ꢎꢛꢊꢚꢎ ꢓꢌꢜꢝ ꢐꢞ ꢟꢋ ꢝꢟ ꢊꢅꢜꢁꢘꢛ ꢋ ꢘꢌ ꢟ ꢅꢒ ꢀ ꢀ ꢛꢋ ꢌꢄ ꢟ  
SCDS135A – SEPTEMBER 2003 − REVISED NOVEMBER 2003  
D
D
D
High-Bandwidth Data Path  
(Up to 500 MHz )  
D
D
Data and Control Inputs Provide  
Undershoot Clamp Diodes  
5-V Tolerant I/Os with Device Powered-Up  
or Powered-Down  
Low Power Consumption  
(I  
= 0.7 mA Typical)  
CC  
Low and Flat ON-State Resistance (r  
)
D
V
Operating Range From 2.3 V to 3.6 V  
on  
CC  
Characteristics Over Operating Range  
(r = 4 Typical)  
D
Data I/Os Support 0- to 5-V Signaling  
Levels (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V,  
5 V)  
on  
D
Rail-to-Rail Switching on Data I/O Ports  
− 0- to 5-V Switching With 3.3-V V  
− 0- to 3.3-V Switching With 2.5-V V  
CC  
CC  
D
D
D
D
Control Inputs Can be Driven by TTL or  
5-V/3.3-V CMOS Outputs  
D
D
Bidirectional Data Flow, With Near-Zero  
Propagation Delay  
I
Supports Partial-Power-Down Mode  
off  
Operation  
Low Input/Output Capacitance Minimizes  
Loading and Signal Distortion  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
(C  
= 3.5 pF Typical)  
io(OFF)  
ESD Performance Tested Per JESD 22  
− 2000-V Human-Body Model  
(A114-B, Class II)  
D
Fast Switching Frequency (f  
Max)  
= 20 MHz  
OE  
For additional information regarding the performance  
characteristics of the CB3Q family, refer to the TI  
application report, CBT-C, CB3T, and CB3Q  
Signal-Switch Families, literature number SCDA008.  
− 1000-V Charged-Device Model (C101)  
D
Supports Both Digital and Analog  
Applications: USB Interface, Differential  
Signal Interface, Bus Isolation,  
Low-Distortion Signal Gating  
DBQ, DGV, OR PW PACKAGE  
(TOP VIEW)  
RGY PACKAGE  
(TOP VIEW)  
V
1
2
3
4
5
6
7
8
16  
S
1B1  
1B2  
1A  
2B1  
2B2  
2A  
CC  
15 OE  
14 4B1  
13 4B2  
12 4A  
1
16  
1B1  
1B2  
1A  
2B1  
2B2  
2A  
15  
14  
13  
12  
11  
10  
2
3
4
5
6
7
OE  
4B1  
4B2  
4A  
3B1  
3B2  
11  
10  
9
3B1  
3B2  
3A  
GND  
8
9
description/ordering information  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
QFN − RGY  
Tape and reel SN74CB3Q3257RGYR  
BU257  
SSOP (QSOP) − DBQ Tape and reel SN74CB3Q3257DBQR  
BU257  
−40°C to 85°C  
TSSOP − PW  
TVSOP − DGV  
Tape and reel SN74CB3Q3257PWR  
Tape and reel SN74CB3Q3257DGVR  
BU257  
BU257  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢌꢫ  
Copyright 2003, Texas Instruments Incorporated  
ꢧ ꢫ ꢨ ꢧꢠ ꢡꢴ ꢣꢢ ꢦ ꢮꢮ ꢬꢦ ꢤ ꢦ ꢥ ꢫ ꢧ ꢫ ꢤ ꢨ ꢙ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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