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SN74AUP1G02_08 PDF预览

SN74AUP1G02_08

更新时间: 2024-11-02 05:24:51
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德州仪器 - TI 输入元件
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16页 492K
描述
LOW-POWER SINGLE 2-INPUT POSITIVE-NOR GATE

SN74AUP1G02_08 数据手册

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SN74AUP1G02  
LOW-POWER SINGLE 2-INPUT POSITIVE-NOR GATE  
www.ti.com  
SCES568DJUNE 2004REVISED MAY 2007  
FEATURES  
Available in the Texas Instruments  
NanoFree™ Package  
Optimized for 3.3-V Operation  
3.6-V I/O Tolerant to Support Mixed-Mode  
Signal Operation  
Low Static-Power Consumption  
(ICC = 0.9 µA Max)  
tpd = 4.5 ns Max at 3.3 V  
Low Dynamic-Power Consumption  
(Cpd = 4.3 pF Typ at 3.3 V)  
Suitable for Point-to-Point Applications  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Low Input Capacitance (Ci = 1.5 pF Typ)  
Low Noise – Overshoot and Undershoot  
<10% of VCC  
ESD Performance Tested Per JESD 22  
2000-V Human-Body Model  
(A114-B, Class II)  
Ioff Supports Partial-Power-Down Mode  
Operation  
200-V Machine Model (A115-A)  
Input Hysteresis Allows Slow Input Transition  
and Better Switching-Noise Immunity at the  
Input (Vhys = 250 mV Typ at 3.3 V)  
1000-V Charged-Device Model (C101)  
ESD Protection Exceeds ±5000 V With  
Human-Body Model  
Wide Operating VCC Range of 0.8 V to 3.6 V  
VCC  
VCC  
A
B
A
B
A
B
VCC  
GND  
Y
Y
GND  
GND  
Y
DRY PACKAGE  
(TOP VIEW)  
YZP PACKAGE  
(BOTTOM VIEW)  
YFP PACKAGE  
(BOTTOM VIEW)  
3
2
1
4
5
6
3
4
Y
GND  
B
GND  
B
Y
VCC  
NC  
Y
1
2
3
6
5
4
A
B
DNU  
VCC  
2
1
A
5
A
VCC  
GND  
See mechanical drawings for dimensions.  
NC - No internal connection  
DNU - Do not use  
DESCRIPTION/ORDERING INFORMATION  
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable  
applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range  
of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal  
integrity (see Figure 1 and Figure 2).  
Y = A + B or Y = A • B  
This single 2-input positive-NOR gate performs the Boolean function  
in positive logic.  
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the  
package.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoFree is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2004–2007, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

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