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SN74AUP1G04 PDF预览

SN74AUP1G04

更新时间: 2024-02-26 00:33:42
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
12页 235K
描述
LOW POWER SINGLE INVERTER GATE

SN74AUP1G04 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:BGA包装说明:VFBGA, BGA5,2X3,20
针数:5Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.63
系列:AUP/ULP/VJESD-30 代码:R-XBGA-B5
长度:1.4 mm负载电容(CL):30 pF
逻辑集成电路类型:INVERTER最大I(ol):0.0017 A
功能数量:1输入次数:1
端子数量:5最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:VFBGA封装等效代码:BGA5,2X3,20
封装形状:RECTANGULAR封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:1.2/3.3 VProp。Delay @ Nom-Sup:19 ns
传播延迟(tpd):19 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:0.5 mm
子类别:Gates最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):0.8 V标称供电电压 (Vsup):1.2 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:BALL
端子节距:0.5 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:0.9 mm
Base Number Matches:1

SN74AUP1G04 数据手册

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ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢃ  
ꢊ ꢋꢌꢍꢆꢋ ꢌ ꢎꢏ ꢀꢐ ꢁꢈ ꢊ ꢎ ꢐꢁ ꢑꢎꢏ ꢒꢎ ꢏ ꢈ ꢄꢒꢎ  
SCES571A − JUNE 2004 − REVISED APRIL 2005  
D
D
D
Available in the Texas Instruments  
NanoStarand NanoFreePackages  
Low Static-Power Consumption;  
D
D
D
D
D
D
Wide Operating V  
Range of 0.8 V to 3.6 V  
CC  
Optimized for 3.3-V Operation  
3.6-V I/O Tolerant to Support Mixed-Mode  
Signal Operation  
I
= 0.9-µA Max  
CC  
Low Dynamic-Power Consumption;  
= 4.1 pF Typical at 3.3 V  
t
= 3.9 ns Max at 3.3 V  
pd  
C
pd  
Suitable for Point-to-Point Applications  
D
Low Input Capacitance; C = 1.5 pF Typical  
i
Low Noise − Overshoot and Undershoot  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
D
<10% of V  
CC  
D
ESD Performance Tested Per JESD 22  
− 2000-V Human-Body Model  
(A114-B, Class II)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
D
D
I
Supports Partial-Power-Down Mode  
off  
Operation  
Input Hysteresis Allows Slow Input  
Transition and Better Switching Noise  
Immunity at the Input  
D
ESD Protection Exceeds 5000-V With  
Human-Body Model  
(V  
= 250 mV Typical at 3.3 V)  
hys  
DBV, DCK, OR DRL PACKAGE  
(TOP VIEW)  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
3 4  
2
GND  
A
DNU  
Y
V
1
2
3
5
4
NC  
A
GND  
V
Y
CC  
1 5  
CC  
DNU − Do not use  
NC − No internal connection  
description/ordering information  
The AUP family is TI’s premier solution to the industry’s low power needs in battery-powered portable  
applications. This family ensures a very low static and dynamic power consumption across the entire V range  
CC  
of 0.8 V to 3.6 V resulting in an increased battery life. This product also maintains excellent signal integrity (see  
Figures 1 and 2).  
Switching Characteristics  
Static-Power Consumption  
Dynamic-Power Consumption  
(pF)  
100%  
at 25 MHz  
(µA)  
3.5  
3
100%  
80%  
60%  
80%  
2.5  
2
Input  
Output  
60%  
40%  
3.3-V  
3.3-V  
†  
Logic  
1.5  
1
Logic  
40%  
0.5  
0
20%  
0%  
20%  
0%  
AUP  
AUP  
−0.5  
10  
15 20  
Time − ns  
0
5
25  
35 40 45  
30  
Single, dual, and triple gates.  
AUP1G08 data at C = 15 pF.  
L
Figure 2. Excellent Signal Integrity  
Figure 1. AUP−The Lowest-Power Family  
This single inverter gate performs the Boolean function Y = A.  
NanoStarand NanoFreepackage technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar and NanoFree are trademarks of Texas Instruments.  
ꢒꢠ  
Copyright 2005, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74AUP1G04 替代型号

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