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SN74AUP1G00DBVRG4 PDF预览

SN74AUP1G00DBVRG4

更新时间： 2024-11-02 03:44:23
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德州仪器 - TI 输入元件
页数 文件大小 规格书
17页 552K
描述
LOW-POWER SINGLE 2-INPUT POSITIVE-NAND GATE

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SN74AUP1G00DBVRG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOT-23
包装说明：LSSOP, TSOP5/6,.11,37针数：5
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.37系列：AUP/ULP/V
JESD-30 代码：R-PDSO-G5JESD-609代码：e4
长度：2.9 mm负载电容（CL）：30 pF
逻辑集成电路类型：NAND GATE最大I（ol）：0.0017 A
湿度敏感等级：1功能数量：1
输入次数：2端子数量：5
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LSSOP封装等效代码：TSOP5/6,.11,37
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
包装方法：TR峰值回流温度（摄氏度）：260
电源：1.2/3.3 VProp。Delay @ Nom-Sup：27.1 ns
传播延迟（tpd）：27.1 ns认证状态：Not Qualified
施密特触发器：NO座面最大高度：1.45 mm
子类别：Gates最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：0.8 V标称供电电压 (Vsup)：1.2 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.95 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：1.6 mmBase Number Matches：1

SN74AUP1G00DBVRG4 数据手册

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SN74AUP1G00  
LOW-POWER SINGLE 2-INPUT POSITIVE-NAND GATE  
www.ti.com  
SCES604E–SEPTEMBER 2004–REVISED MAY 2007  
FEATURES  
•
•
•
Available in the Texas Instruments  
NanoFree™ Package  
•
•
Optimized for 3.3-V Operation  
3.6-V I/O Tolerant to Support Mixed-Mode  
Signal Operation  
Low Static-Power Consumption  
(ICC = 0.9 µA Max)  
•
•
•
tpd = 4.8 ns Max at 3.3 V  
Low Dynamic-Power Consumption  
(Cpd = 4 pF Typ at 3.3 V)  
Suitable for Point-to-Point Applications  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
•
•
Low Input Capacitance (Ci = 1.5 pF Typ)  
Low Noise Overshoot and Undershoot  
<10% of VCC  
•
ESD Performance Tested Per JESD 22  
–
2000-V Human-Body Model  
(A114-B, Class II)  
•
•
Ioff Supports Partial-Power-Down Mode  
Operation  
–
–
200-V Machine Model (A115-A)  
Input Hysteresis Allows Slow Input Transition  
and Better Switching Noise Immunity at Input  
(Vhys = 250 mV Typ at 3.3 V)  
1000-V Charged-Device Model (C101)  
•
ESD Protection Exceeds ±5000 V With  
Human-Body Model  
•
Wide Operating VCC Range of 0.8 V to 3.6 V  
YFP PACKAGE  
(BOTTOM VIEW)  
DRY PACKAGE  
(TOP VIEW)  
GND  
1
2
3
6
5
4
A
B
VCC  
NC  
Y
DNU  
VCC  
6
A
GND  
DNU – Do not use  
NC – No internal connection  
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable  
applications. This family ensures a very low static and dynamic power consumption across the entire VCC range  
of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see  
Figure 1 and Figure 2).  
This single 2-input positive-NAND gate performs the Boolean function Y = A • B or Y = A + B in positive logic.  
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the  
package.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoFree is a trademark of Texas Instruments.  
UNLESS OTHERWISE NOTED this document contains  
Copyright © 2004–2007, Texas Instruments Incorporated  
PRODUCTION DATA information current as of publication date.  
Products conform to specifications per the terms of Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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SN74AUP1G00DBVRG4 替代型号

型号 品牌 替代类型 描述 数据表
SN74AUP1G00DBVTG4 TI

完全替代

 LOW-POWER SINGLE 2-INPUT POSITIVE-NAND GATE
SN74AUP1G00DBVRE4 TI

完全替代

 LOW-POWER SINGLE 2-INPUT POSITIVE-NAND GATE
SN74AUP1G00DBVR TI

类似代替

 LOW-POWER SINGLE 2-INPUT POSITIVE-NAND GATE

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