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SN74AUC74RGYRG4 PDF预览

SN74AUC74RGYRG4

更新时间： 2024-11-16 05:17:39
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路
页数 文件大小 规格书
12页 560K
描述
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

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SN74AUC74RGYRG4 技术参数

是否Rohs认证：符合生命周期：Obsolete
零件包装代码：QFN包装说明：QFN-14
针数：14Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.59
Is Samacsys：N系列：AUC
JESD-30 代码：S-PQCC-N14JESD-609代码：e4
长度：3.5 mm负载电容（CL）：15 pF
逻辑集成电路类型：D FLIP-FLOP最大频率@ Nom-Sup：225000000 Hz
最大I（ol）：0.005 A湿度敏感等级：2
位数：1功能数量：2
端子数量：14最高工作温度：85 °C
最低工作温度：-40 °C输出极性：COMPLEMENTARY
封装主体材料：PLASTIC/EPOXY封装代码：HVQCCN
封装等效代码：LCC14/18,.14SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：260电源：1.2/2.5 V
Prop。Delay @ Nom-Sup：4 ns传播延迟（tpd）：4 ns
认证状态：Not Qualified座面最大高度：1 mm
子类别：FF/Latches最大供电电压 (Vsup)：2.7 V
最小供电电压 (Vsup)：0.8 V标称供电电压 (Vsup)：1.2 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：3.5 mm
最小 fmax：350 MHzBase Number Matches：1

SN74AUC74RGYRG4 数据手册

 浏览型号SN74AUC74RGYRG4的Datasheet PDF文件第2页浏览型号SN74AUC74RGYRG4的Datasheet PDF文件第3页浏览型号SN74AUC74RGYRG4的Datasheet PDF文件第4页浏览型号SN74AUC74RGYRG4的Datasheet PDF文件第5页浏览型号SN74AUC74RGYRG4的Datasheet PDF文件第6页浏览型号SN74AUC74RGYRG4的Datasheet PDF文件第7页 
SN74AUC74  
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH CLEAR AND PRESET  
www.ti.com  
SCES483A–AUGUST 2003–REVISED MARCH 2005  
FEATURES  
RGY PACKAGE  
(TOP VIEW)  
•
Optimized for 1.8-V Operation and Is 3.6-V I/O  
Tolerant to Support Mixed-Mode Signal  
Operation  
•
Ioff Supports Partial-Power-Down Mode  
Operation  
1
14  
13  
12  
11  
10  
9
1D  
1CLK  
1PRE  
1Q  
2CLR  
2D  
2
3
4
5
6
•
•
•
•
•
Sub-1-V Operable  
Max tpd of 1.8 ns at 1.8 V  
2CLK  
2PRE  
2Q  
Low Power Consumption, 10-µA Max ICC  
±8-mA Output Drive at 1.8 V  
1Q  
7
8
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
•
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
DESCRIPTION/ORDERING INFORMATION  
This dual positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically  
for 1.65-V to 1.95-V VCC operation.  
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the  
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time  
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs  
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,  
data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for  
higher frequencies, the CLR input overrides the PRE input when they are both low.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING  
–40°C to 85°C  
QFN – RGY  
Tape and reel  
SN74AUC74RGYR  
MS74  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
PRE  
L
CLR  
CLK  
D
X
X
H
L
Q
H
L
Q
L
H
L
X
X
↑
X
H
H
H
H
H
H
L
L
H
↑
H
H
L
X
Q0  
Q 0  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...12

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SN74AUC74RGYRG4 替代型号

型号 品牌 替代类型 描述 数据表
SN74AUC74RGYR TI

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 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

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