Datasheet > 逻辑 > 总线驱动器/收发器> SN74AUCH32374

SN74AUCH32374

更新时间： 2024-11-15 22:36:07

品牌	Logo	应用领域
德州仪器 - TI		触发器输出元件
页数	文件大小	规格书
11页	285K
描述
32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

SN74AUCH32374 数据手册

SN74AUCH32374

32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP

WITH 3-STATE OUTPUTS

SCES476 – AUGUST 2003

Member of the Texas Instruments

8-mA Output Drive at 1.8 V

Widebus+ Family

Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

Optimized for 1.8-V Operation and is 3.6-V

I/O Tolerant to Support Mixed-Mode Signal

Operation

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

Supports Partial-Power-Down Mode

off

Operation

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

Sub 1-V Operable

Max t of 2.8 ns at 1.8 V

Low Power Consumption, 40-µA Max I

– 1000-V Charged-Device Model (C101)

description/ordering information

This 32-bit edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V V , but is designed specifically for

1.65-V to 1.95-V V

operation.

The SN74AUCH32374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus

drivers, and working registers. It can be used as four 8-bit flip-flops, two 16-bit flip-flops, or one 32-bit flip-flop.

On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up

at the data (D) inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high

or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive

thebuslinessignificantly. Thehigh-impedancestateandincreaseddriveprovidethecapabilitytodrivebuslines

without interface or pullup components.

OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while

the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Activebus-holdcircuitryholdsunusedorundriveninputsatavalidlogicstate. Useofpulluporpulldownresistors

with the bus-hold circuitry is not recommended.

This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,

off

preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

–40°C to 85°C LFBGA – GKE Tape and reel

SN74AUCH32374GKER

MK374

†

Packagedrawings,standardpackingquantities,thermaldata,symbolization,andPCBdesignguidelines

are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus+ is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...11

中文翻译

下载PDF

与SN74AUCH32374相关器件

型号	品牌	获取价格	描述	数据表
SN74AUCH32374GKER	TI	获取价格	32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74AUCH32374ZKER	TI	获取价格	32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74AUCU04	TI	获取价格	HEX INVERTER
SN74AUCU04RGYR	TI	获取价格	HEX INVERTER
SN74AUCU04RGYRG4	TI	获取价格	AUC SERIES, HEX 1-INPUT INVERT GATE, PQCC14, GREEN, PLASTIC, MO-241BA, QFN-14
SN74AUP1G	TI	获取价格	TEXAS(德州)逻辑电路型号列表(2007).
SN74AUP1G00	TI	获取价格	LOW-POWER SINGLE 2-INPUT POSITIVE-NAND GATE
SN74AUP1G00_07	TI	获取价格	LOW-POWER SINGLE 2-INPUT POSITIVE-NAND GATE
SN74AUP1G00_101	TI	获取价格	LOW-POWER SINGLE 2-INPUT POSITIVE-NAND GATE
SN74AUP1G00DBVR	TI	获取价格	LOW-POWER SINGLE 2-INPUT POSITIVE-NAND GATE

与SN74AUCH32374相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

14
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

7
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

36
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

31

产品中心

服务支持

精选活动

关于我们

帮助中心

SN74AUCH32374

SN74AUCH32374 数据手册

与SN74AUCH32374相关器件

与SN74AUCH32374相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

SN74AUCH32374

SN74AUCH32374 数据手册

与SN74AUCH32374相关器件

与SN74AUCH32374相关文章

您还可以找

您在本页遇到什么问题？