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SN74AUC74RGYR PDF预览

SN74AUC74RGYR

更新时间： 2024-09-28 22:16:39
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路
页数 文件大小 规格书
7页 146K
描述
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

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中文翻译

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SN74AUC74RGYR 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：QFN
包装说明：QFN-14针数：14
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.5Is Samacsys：N
系列：AUCJESD-30 代码：S-PQCC-N14
JESD-609代码：e4长度：3.5 mm
负载电容（CL）：15 pF逻辑集成电路类型：D FLIP-FLOP
最大频率@ Nom-Sup：225000000 Hz最大I（ol）：0.009 A
湿度敏感等级：2位数：1
功能数量：2端子数量：14
最高工作温度：85 °C最低工作温度：-40 °C
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：HVQCCN封装等效代码：LCC14/18,.14SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
包装方法：TR峰值回流温度（摄氏度）：260
电源：1.2/2.5 V最大电源电流（ICC）：0.01 mA
Prop。Delay @ Nom-Sup：4 ns传播延迟（tpd）：4 ns
认证状态：Not Qualified座面最大高度：1 mm
子类别：FF/Latches最大供电电压 (Vsup)：2.7 V
最小供电电压 (Vsup)：0.8 V标称供电电压 (Vsup)：1.2 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：3.5 mm
最小 fmax：350 MHzBase Number Matches：1

SN74AUC74RGYR 数据手册

 浏览型号SN74AUC74RGYR的Datasheet PDF文件第2页浏览型号SN74AUC74RGYR的Datasheet PDF文件第3页浏览型号SN74AUC74RGYR的Datasheet PDF文件第4页浏览型号SN74AUC74RGYR的Datasheet PDF文件第5页浏览型号SN74AUC74RGYR的Datasheet PDF文件第6页浏览型号SN74AUC74RGYR的Datasheet PDF文件第7页 
SN74AUC74  
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS  
WITH CLEAR AND PRESET  
SCES483 – AUGUST 2003  
RGY PACKAGE  
(TOP VIEW)  
Optimized for 1.8-V Operation and Is 3.6-V  
I/O Tolerant to Support Mixed-Mode Signal  
Operation  
I
Supports Partial-Power-Down Mode  
off  
Operation  
1
14  
Sub 1-V Operable  
1D  
1CLK  
1PRE  
1Q  
13 2CLR  
12 2D  
2
3
4
5
6
Max t of 1.8 ns at 1.8-V  
pd  
Low Power Consumption, 10-µA Max I  
11  
10  
9
2CLK  
2PRE  
2Q  
CC  
8-mA Output Drive at 1.8 V  
1Q  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
7
8
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
description/ordering information  
Thisdualpositive-edge-triggeredD-typeflip-flopisoperationalat0.8-Vto2.7-VV ,butisdesignedspecifically  
CC  
for 1.65-V to 1.95-V V  
operation.  
CC  
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the  
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time  
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs  
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,  
data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop  
for higher frequencies, the CLR input overrides the PRE input when they are both low.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
–40°C to 85°C QFN – RGY  
Tape and reel  
SN74AUC74RGYR  
MS74  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
PRE  
L
CLR  
CLK  
X
D
X
X
H
L
Q
H
L
Q
L
H
L
X
X
H
L
H
H
H
H
↑
H
L
H
↑
H
H
L
X
Q
Q
0
0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

中文翻译

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SN74AUC74RGYR 替代型号

型号 品牌 替代类型 描述 数据表
SN74AUC74RGYRG4 TI

类似代替

 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
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功能相似

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