5秒后页面跳转
捷配首页

Datasheet > SN74ALVTH16841DGVR
SN74ALVTH16841DGVR PDF预览

SN74ALVTH16841DGVR

更新时间： 2024-11-05 06:47:15
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件电视
页数 文件大小 规格书
9页 143K
描述
ALVT SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56, PLASTIC, TVSOP-56

阅读下载

中文翻译

获取价格

SN74ALVTH16841DGVR 数据手册

 浏览型号SN74ALVTH16841DGVR的Datasheet PDF文件第2页浏览型号SN74ALVTH16841DGVR的Datasheet PDF文件第3页浏览型号SN74ALVTH16841DGVR的Datasheet PDF文件第4页浏览型号SN74ALVTH16841DGVR的Datasheet PDF文件第5页浏览型号SN74ALVTH16841DGVR的Datasheet PDF文件第6页浏览型号SN74ALVTH16841DGVR的Datasheet PDF文件第7页 
SN54ALVTH16841, SN74ALVTH16841  
2.5-V/3.3-V 20-BIT BUS-INTERFACE D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCES077B – JULY 1996 – REVISED JULY 1997  
SN54ALVTH16841 . . . WD PACKAGE  
SN74ALVTH16841 . . . DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
High-Impedance State During Power Up  
and Power Down  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
1LE  
1D1  
1D2  
GND  
1D3  
1D4  
1
2
3
4
5
6
7
8
9
56  
55  
54  
53  
52  
51  
50  
49  
48  
5-V I/O Compatible  
High-Drive Capability (–32 mA/64 mA)  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
CC  
A
Auto 3-State Eliminates Bus Current  
Loading When Voltage at the Output  
V
V
CC  
CC  
1Q5  
1D5  
Exceeds V  
CC  
1Q6  
1D6  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
1Q7 10  
47 1D7  
GND  
1Q8  
GND  
1D8  
11  
12  
46  
45  
Power Off Disables Inputs/Outputs,  
Permitting Live Insertion  
1Q9 13  
1Q10 14  
2Q1 15  
2Q2 16  
44 1D9  
43 1D10  
42 2D1  
41 2D2  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL), Thin Shrink  
Small-Outline (DGG), Thin Very  
2Q3  
17  
40  
2D3  
Small-Outline (DGV) Packages, and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
GND 18  
2Q4 19  
2Q5 20  
2Q6 21  
39 GND  
38 2D4  
37 2D5  
36 2D6  
description  
V
22  
35  
V
CC  
CC  
The ’ALVTH16841 are 20-bit bus-interface D-type  
latches with 3-state outputs designed for 2.5-V or  
2Q7 23  
2Q8 24  
GND 25  
2Q9 26  
2Q10 27  
2OE 28  
34 2D7  
33 2D8  
32 GND  
31 2D9  
30 2D10  
29 2LE  
3.3-V V  
operation, but with the capability to  
CC  
provide a TTL interface to a 5-V system  
environment.  
The ’ALVTH16841 features 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. This device is  
particularly suitable for implementing buffer  
registers, unidirectional bus drivers, and working  
registers.  
The ’ALVTH16841 can be used as two 10-bit latches or one 20-bit latch. The 20 latches are transparent D-type  
latches. Thedevicehasnoninvertingdata(D)inputsandprovidestruedataatitsoutputs. Whilethelatch-enable  
(1LE or 2LE) input is high, the Q outputs of the corresponding 10-bit latch follow the D inputs. When LE is taken  
low, the Q outputs are latched at the levels set up at the D inputs.  
A buffered output-enable (1OE or 2OE) input can be used to place the outputs of the corresponding 10-bit latch  
in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state,  
the outputs neither load nor drive the bus lines significantly.  
The output-enable (OE) input does not affect the internal operation of the latches. Old data can be retained or  
new data can be entered while the outputs are in the high-impedance state.  
Active bus-hold circuitry is provided to hold unused or floating inputs at a valid logic level.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

中文翻译

下载PDF

与SN74ALVTH16841DGVR相关器件

型号 品牌 获取价格 描述 数据表
SN74ALVTH16841DL TI

获取价格

 		ALVT SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56, 0.300 INCH, PLASTIC, SSOP-56
SN74ALVTH16841DLR TI

获取价格

 		ALVT SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56, 0.300 INCH, PLASTIC, SSOP-56
SN74ALVTH32244 TI

获取价格

 		2.5-V/3.3-V 32-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN74ALVTH32244GKE TI

获取价格

 		暂无描述
SN74ALVTH32244KR TI

获取价格

 		2.5-V/3.3-V 32-Bit Buffers/Drivers With 3-State outputs 96-LFBGA -40 to 85
SN74ALVTH32373 TI

获取价格

 		2.5-V/3.3-V 32-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74ALVTH32373GKE TI

获取价格

 		ALVT SERIES, QUAD 8-BIT DRIVER, TRUE OUTPUT, PBGA96, PLASTIC, FBGA-96
SN74ALVTH32373KR TI

获取价格

 		2.5-V/3.3-V 32-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74ALVTH32374 TI

获取价格

 		2.5-V/3.3-V 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74ALVTHR16245 TI

获取价格

 		2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

与SN74ALVTH16841DGVR相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证