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SN74ALVCH374PW

更新时间： 2024-09-15 23:09:43
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
9页 126K
描述
OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

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SN74ALVCH374PW 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP-20针数：20
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：5.47
Is Samacsys：N控制类型：INDEPENDENT CONTROL
计数方向：UNIDIRECTIONAL系列：ALVC/VCX/A
JESD-30 代码：R-PDSO-G20JESD-609代码：e4
长度：6.5 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.024 A
湿度敏感等级：1位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP20,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TUBE峰值回流温度（摄氏度）：260
电源：3.3 V最大电源电流（ICC）：0.01 mA
Prop。Delay @ Nom-Sup：3.6 ns传播延迟（tpd）：6.4 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：FF/Latches最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A触发器类型：POSITIVE EDGE
宽度：4.4 mmBase Number Matches：1

SN74ALVCH374PW 数据手册

 浏览型号SN74ALVCH374PW的Datasheet PDF文件第2页浏览型号SN74ALVCH374PW的Datasheet PDF文件第3页浏览型号SN74ALVCH374PW的Datasheet PDF文件第4页浏览型号SN74ALVCH374PW的Datasheet PDF文件第5页浏览型号SN74ALVCH374PW的Datasheet PDF文件第6页浏览型号SN74ALVCH374PW的Datasheet PDF文件第7页 
SN74ALVCH374  
OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH 3-STATE OUTPUTS  
SCES118E – JULY 1997 – REVISED OCTOBER 1999  
DGV, DW, OR PW PACKAGE  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
(TOP VIEW)  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
8Q  
8D  
1
2
3
4
5
6
7
8
9
20  
19  
18  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
17 7D  
16 7Q  
15 6Q  
14 6D  
13 5D  
12 5Q  
11 CLK  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
GND 10  
Package Options Include Plastic  
Small-Outline (DW), Thin Very  
Small-Outline (DGV), and Thin Shrink  
Small-Outline (PW) Packages  
description  
This octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V V  
operation.  
CC  
The SN74ALVCH374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus  
drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the  
logic levels at the data (D) inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive  
thebuslinessignificantly. Thehigh-impedancestateandincreaseddriveprovidethecapabilitytodrivebuslines  
without interface or pullup components.  
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while  
the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVCH374 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUT  
Q
OE  
L
CLK  
D
H
L
↑
↑
H
L
L
L
H or L  
X
X
X
Q
0
H
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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SN74ALVCH374PW 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALVCH374DGVR TI

完全替代

 Octal Positive-Edge-Triggered D-Type Flip-Flop With 3-State Outputs 20-TVSOP -40 to 85

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