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SN74ALVC16834DL PDF预览

SN74ALVC16834DL

更新时间: 2024-11-05 23:09:43
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器输出元件
页数 文件大小 规格书
10页 151K
描述
18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

SN74ALVC16834DL 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP, SSOP56,.4针数:56
Reach Compliance Code:unknownHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.81
控制类型:ENABLE LOW系列:ALVC/VCX/A
JESD-30 代码:R-PDSO-G56JESD-609代码:e4
长度:18.415 mm逻辑集成电路类型:BUS DRIVER
最大I(ol):0.024 A湿度敏感等级:1
位数:18功能数量:1
端口数量:2端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP56,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH包装方法:TUBE
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:4.6 ns传播延迟(tpd):6 ns
认证状态:Not Qualified座面最大高度:2.79 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.49 mm

SN74ALVC16834DL 数据手册

 浏览型号SN74ALVC16834DL的Datasheet PDF文件第2页浏览型号SN74ALVC16834DL的Datasheet PDF文件第3页浏览型号SN74ALVC16834DL的Datasheet PDF文件第4页浏览型号SN74ALVC16834DL的Datasheet PDF文件第5页浏览型号SN74ALVC16834DL的Datasheet PDF文件第6页浏览型号SN74ALVC16834DL的Datasheet PDF文件第7页 
SN74ALVC16834  
18-BIT UNIVERSAL BUS DRIVER  
WITH 3-STATE OUTPUTS  
SCES140B – JULY 1998 – REVISED FEBRUARY 1999  
DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
NC  
NC  
Y1  
GND  
Y2  
Y3  
GND  
NC  
A1  
GND  
A2  
A3  
2
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
3
4
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
5
6
7
V
V
CC  
Y4  
CC  
8
A4  
A5  
A6  
GND  
A7  
Package Options Include Plastic Shrink  
Small-Outline (DL), Thin Shrink  
Small-Outline (DGG), and Thin Very  
Small-Outline (DGV) Packages  
9
Y5  
Y6  
GND  
Y7  
Y8  
Y9  
Y10  
Y11  
Y12  
GND  
Y13  
Y14  
Y15  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
description  
A8  
A9  
This 18-bit universal bus driver is designed for  
1.65-V to 3.6-V V operation.  
A10  
A11  
A12  
GND  
A13  
A14  
A15  
CC  
Data flow from A to Y is controlled by the  
output-enable (OE) input. The device operates in  
the transparent mode when the latch-enable (LE)  
inputislow. TheAdataislatchediftheclock(CLK)  
input is held at a high or low logic level. If LE is  
high, the A data is stored in the latch/flip-flop on  
the low-to-high transition of CLK. When OE is  
high, the outputs are in the high-impedance state.  
V
V
CC  
CC  
Y16  
Y17  
GND  
Y18  
OE  
A16  
A17  
GND  
A18  
CLK  
GND  
To ensure the high-impedance state during power  
up or power down, OE should be tied to V  
CC  
through a pullup resistor; the minimum value of  
the resistor is determined by the current-sinking  
capability of the driver.  
LE  
NC – No internal connection  
The SN74ALVC16834 is characterized for  
operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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