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SN74ALVC16901DGGR PDF预览

SN74ALVC16901DGGR

更新时间： 2024-11-26 19:51:19
品牌 Logo 应用领域
德州仪器 - TI 光电二极管逻辑集成电路
页数 文件大小 规格书
9页 160K
描述
18-Bit Universal Bus Transceiver with Parity Generators/Checkers 64-TSSOP -40 to 85

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SN74ALVC16901DGGR 技术参数

是否无铅： 含铅生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP,
针数：64Reach Compliance Code：unknown
风险等级：5.84系列：ALVC/VCX/A
JESD-30 代码：R-PDSO-G64长度：17 mm
逻辑集成电路类型：BUS TRANSCEIVER位数：9
功能数量：2端口数量：2
端子数量：64最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟（tpd）：7 ns
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.3 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL宽度：6.1 mm
Base Number Matches：1

SN74ALVC16901DGGR 数据手册

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SCAS276A − NOVEMBER 1993 − REVISED JULY 1995  
DGG PACKAGE  
(TOP VIEW)  
D Member of the Texas Instruments  
Widebus+Family  
D EPIC (Enhanced-Performance Implanted  
D UBT (Universal Bus Transceiver)  
Combines D-Type Latches and D-Type  
Flip-Flops for Operation in Transparent,  
Latched, or Clocked Mode  
1CLKENAB  
LEAB  
CLKAB  
1ERRA  
1APAR  
GND  
1CLKENBA  
LEBA  
CLKBA  
1ERRB  
1BPAR  
GND  
1B1  
1B2  
1B3  
1
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33  
CMOS) Submicron Process  
2
3
4
5
6
D Simultaneously Generates and Checks  
1A1  
1A2  
1A3  
7
Parity  
8
D Option to Select Generate Parity and Check  
or Feed-Through Data/Parity in A-to-B or  
B-to-A Directions  
9
V
V
10  
11  
12  
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CC  
CC  
1A4  
1A5  
1A6  
GND  
1A7  
1A8  
2A1  
2A2  
GND  
2A3  
2A4  
2A5  
1B4  
1B5  
1B6  
GND  
1B7  
1B8  
2B1  
2B2  
GND  
2B3  
2B4  
2B5  
D Distributed V  
and GND Pin Configuration  
Minimizes High-Speed Switching Noise  
CC  
D Latch-Up Performance Exceeds 250 mA  
Per JEDEC Standard JESD-17  
D Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
D Packaged in Thin Shrink Small-Outline  
(DGG) Package  
description  
V
V
CC  
CC  
2A6  
2A7  
2A8  
GND  
2B6  
2B7  
2B8  
GND  
2BPAR  
2ERRB  
OEBA  
ODD/EVEN  
2CLKENBA  
This 18-bit (dual-octal) noninverting registered  
transceiver is designed for 2.7-V to 3.6-V V  
operation.  
CC  
The SN74ALVC16901 is a dual 9-bit to dual 9-bit  
parity transceiver with registers. The device can  
operate as a feed-through transceiver or it can  
generate/check parity from the two 8-bit data  
buses in either direction.  
2APAR  
2ERRA  
OEAB  
SEL  
2CLKENAB  
The SN74ALVC16901 features independent  
clock (CLKAB or CLKBA), latch-enable (LEAB or  
LEBA), and dual 9-bit clock-enable (CLKENAB or  
CLKENBA) inputs. It also provides parity-enable (SEL) and parity-select (ODD/EVEN) inputs and separate  
error-signal (ERRA or ERRB) outputs for checking parity. The direction of data flow is controlled by OEAB and  
OEBA. When SEL is low, the parity functions are enabled. When SEL is high, the parity functions are disabled  
and the device acts as an 18-bit registered transceiver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVC16901 is available in TI’s thin shrink small-outline (DGG) package, which provides twice the I/O  
pin count and functionality of standard small-outline packages in the same printed-circuit-board area.  
The SN74ALVC16901 is characterized for operation from −40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus+, EPIC, and UBT are trademarks of Texas Instruments Incorporated.  
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ꢤ ꢨ ꢥ ꢤꢝ ꢞꢲ ꢠꢟ ꢣ ꢫꢫ ꢩꢣ ꢡ ꢣ ꢢ ꢨ ꢤ ꢨ ꢡ ꢥ ꢭ  
Copyright 1995, Texas Instruments Incorporated  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...9

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