Datasheet > SN74ALVC00_08

SN74ALVC00_08

更新时间： 2024-11-18 05:24:55

品牌	Logo	应用领域
德州仪器 - TI		输入元件
页数	文件大小	规格书
16页	754K
描述
QUADRUPLE 2-INPUT POSITIVE-NAND GATE

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SN74ALVC00_08 数据手册

SN74ALVC00

QUADRUPLE 2-INPUT POSITIVE-NAND GATE

www.ti.com

SCES115G–JULY 1997–REVISED AUGUST 2004

FEATURES

•

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

•

Operates From 1.65 V to 3.6 V

Max t_pdof 3 ns at 3.3 V

±24-mA Output Drive at 3.3 V

– 1000-V Charged-Device Model (C101)

Latch-Up Performance Exceeds 250 mA Per

JESD 17

D, DGV, NS, OR PW PACKAGE

(TOP VIEW)

RGY PACKAGE

(TOP VIEW)

13 4B

GND

DESCRIPTION/ORDERING INFORMATION

This quadruple 2-input positive-NAND gate is designed for 1.65-V to 3.6-V V_CCoperation.

The SN74ALVC00 performs the Boolean function Y = A · B or Y = A + B in positive logic.

ORDERING INFORMATION

T_A

PACKAGE⁽¹⁾

ORDERABLE PART NUMBER

SN74ALVC00RGYR

SN74ALVC00D

TOP-SIDE MARKING

QFN - RGY

SOIC - D

Tape and reel

VA00

Tube

ALVC00

Tape and reel

SN74ALVC00DR

-40°C to 85°C

SOP - NS

SN74ALVC00NSR

ALVC00

VA00

TSSOP - PW

TVSOP - DGV

SN74ALVC00PWR

SN74ALVC00DGVR

VA00

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...16

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