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SN74ALVC00IDREP PDF预览

SN74ALVC00IDREP

更新时间: 2024-11-19 02:58:39
品牌 Logo 应用领域
德州仪器 - TI 输入元件光电二极管逻辑集成电路触发器
页数 文件大小 规格书
9页 308K
描述
QUADRUPLE 2-INPUT POSITIVE-NAND GATE

SN74ALVC00IDREP 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP14,.25针数:14
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:0.95
系列:ALVC/VCX/AJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:8.65 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.024 A湿度敏感等级:1
功能数量:4输入次数:2
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TR峰值回流温度(摄氏度):260
电源:3.3 V最大电源电流(ICC):0.01 mA
Prop。Delay @ Nom-Sup:3 ns传播延迟(tpd):4.4 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.75 mm子类别:Gates
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.91 mm
Base Number Matches:1

SN74ALVC00IDREP 数据手册

 浏览型号SN74ALVC00IDREP的Datasheet PDF文件第2页浏览型号SN74ALVC00IDREP的Datasheet PDF文件第3页浏览型号SN74ALVC00IDREP的Datasheet PDF文件第4页浏览型号SN74ALVC00IDREP的Datasheet PDF文件第5页浏览型号SN74ALVC00IDREP的Datasheet PDF文件第6页浏览型号SN74ALVC00IDREP的Datasheet PDF文件第7页 
ꢀꢁꢂ ꢃ ꢄ ꢅꢆ ꢇꢈ ꢈꢉ ꢊꢋ  
ꢌ ꢍꢄꢎꢏ ꢍꢋꢅ ꢊ ꢐ ꢉꢑꢁ ꢋꢍꢒ ꢋꢓ ꢀꢑ ꢒ ꢑꢆꢊ ꢉꢁꢄ ꢁꢎ ꢔ ꢄꢒꢊ  
SCES521A − DECEMBER 2003 − REVISED MAY 2004  
D
D
D
D
D
Controlled Baseline  
− One Assembly/Test Site, One Fabrication  
Site  
D
Operates From 1.65 V to 3.6 V  
D
D
D
Max t of 3 ns at 3.3 V  
pd  
24-mA Output Drive at 3.3 V  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Enhanced Product-Change Notification  
D OR PW PACKAGE  
(TOP VIEW)  
Qualification Pedigree  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1A  
1B  
1Y  
2A  
2B  
V
CC  
4B  
4A  
4Y  
3B  
3A  
3Y  
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, Highly  
Accelerated Stress Test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life. Such qualification  
testing should not be viewed as justifying use of this component  
beyond specified performance and environmental limits.  
2Y  
GND  
8
description/ordering informatiom  
The SN74ALVC00 quadruple 2-input positive-NAND gate is designed for 1.65-V to 3.6-V V  
operation.  
CC  
The device performs the Boolean function Y = A B or Y = A + B in positive logic.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
SOIC − D  
Tape and reel  
Tape and reel  
SN74ALVC00IDREP  
SN74ALVC00IPWREP  
ALVC00IEP  
ALVC00E  
−40°C to 85°C  
§
TSSOP − PW  
§
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Product Preview  
FUNCTION TABLE  
(each gate)  
INPUTS  
OUTPUT  
Y
A
B
H
X
L
H
L
L
H
H
X
logic diagram, each gate (positive logic)  
A
B
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢒꢠ  
Copyright 2004, Texas Instruments Incorporated  
ꢜ ꢠ ꢝ ꢜꢕ ꢖꢪ ꢘꢗ ꢛ ꢣꢣ ꢡꢛ ꢙ ꢛ ꢚ ꢠ ꢜ ꢠ ꢙ ꢝ ꢥ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74ALVC00IDREP 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALVC00IDRQ1 TI

完全替代

QUADRUPLE 2-INPUT POSITIVE-NAND GATE
SN74ALVC00IDRG4Q1 TI

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QUADRUPLE 2-INPUT POSITIVE-NAND GATE
SN74LVC08ADR TI

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