Datasheet > SN74ALS323

SN74ALS323

更新时间： 2024-11-22 23:06:15

品牌	Logo	应用领域
德州仪器 - TI		存储输出元件
页数	文件大小	规格书
7页	121K
描述
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH SYNCHRONOUS CLEAR AND 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

数据手册
替代型号

如果您发现信息不准确，欢迎纠错

SN74ALS323 数据手册

SN54ALS323, SN74ALS323

8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS

WITH SYNCHRONOUS CLEAR AND 3-STATE OUTPUTS

SDAS267A – DECEMBER 1982 – REVISED DECEMBER 1994

SN54ALS323 . . . J PACKAGE

SN74ALS323 . . . DW OR N PACKAGE

(TOP VIEW)

• Multiplexed I/O Ports Provide Improved Bit

Density

• Four Modes of Operation:

– Hold (Store)

OE1

OE2

– Shift Right

– Shift Left

– Load Data

G/Q

H′

• Operate With Outputs Enabled or at High

E/Q

H/Q

Impedance

C/Q

F/Q

• 3-State Outputs Drive Bus Lines Directly

• Can Be Cascaded for n-Bit Word Lengths

• Synchronous Clear

A/Q

D/Q

B/Q

A′

CLR

GND

CLK

• Applications:

– Stacked or Push-Down Registers

– Buffer Storage

SN54ALS323 . . . FK PACKAGE

(TOP VIEW)

– Accumulator Registers

• Package Options Include Plastic

Small-Outline (DW) Packages, Ceramic

Chip Carriers (FK), and Standard Plastic (N)

and Ceramic (J) 300-mil DIPs

20 19

G/Q

E/Q

H′

description

C/Q

A/Q

H/Q

F/Q

These 8-bit universal shift/storage registers

feature multiplexed input/output (I/O) ports to

achieve full 8-bit data handling in a 20-pin

package. Two function-select (S0, S1) inputs and

two output-enable (OE1, OE2) inputs can be used

to choose the modes of operation listed in the

function table.

D/Q

A′

9 10 11 12 13

Synchronous parallel loading is accomplished by taking both S0 and S1 high. This places the 3-state outputs

in the high-impedance state and permits data applied on the I/O ports to be clocked into the register. Reading

out of the register can be accomplished while the outputs are enabled in any mode. Clearing occurs

synchronously when the clear (CLR) input is low. Taking either OE1 or OE2 high disables the outputs but has

no effect on clearing, shifting, or storing data.

The SN54ALS323 is characterized for operation over the full military temperature range of –55°C to 125°C. The

SN74ALS323 is characterized for operation from 0°C to 70°C.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7

中文翻译

下载PDF

SN74ALS323 替代型号

型号	品牌	替代类型	描述	数据表
SN54ALS323	TI	功能相似	8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH SYNCHRONOUS CLEAR AND 3-STATE OUTPUTS

与SN74ALS323相关器件

型号	品牌	获取价格	描述	数据表
SN74ALS323DW	TI	获取价格	8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH SYNCHRONOUS CLEAR AND 3-STATE OUTPUTS
SN74ALS323DW3	TI	获取价格	IC,SHIFT REGISTER,ALS-TTL,SOP,20PIN,PLASTIC
SN74ALS323DWE4	TI	获取价格	ALS SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO
SN74ALS323DWG4	TI	获取价格	ALS SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO
SN74ALS323DWP3	TI	获取价格	IC,SHIFT REGISTER,ALS-TTL,SOP,20PIN,PLASTIC
SN74ALS323DWR	TI	获取价格	ALS SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO
SN74ALS323DWRG4	TI	获取价格	ALS SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO
SN74ALS323FN	TI	获取价格	IC,SHIFT REGISTER,ALS-TTL,LDCC,20PIN,PLASTIC
SN74ALS323J4	TI	获取价格	IC,SHIFT REGISTER,ALS-TTL,DIP,20PIN,CERAMIC
SN74ALS323JP4	TI	获取价格	IC,SHIFT REGISTER,ALS-TTL,DIP,20PIN,CERAMIC

与SN74ALS323相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

36
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

28
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

56
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

53

产品中心

服务支持

精选活动

关于我们

帮助中心

SN74ALS323

SN74ALS323 数据手册

SN74ALS323 替代型号

与SN74ALS323相关器件

与SN74ALS323相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

SN74ALS323

SN74ALS323 数据手册

SN74ALS323 替代型号

与SN74ALS323相关器件

与SN74ALS323相关文章

您还可以找

您在本页遇到什么问题？