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SN74AHCT74MPWREP

更新时间： 2024-09-14 11:06:19
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器
页数 文件大小 规格书
9页 434K
描述
具有清零和预置端的增强型产品双路正边沿触发式 D 型触发器 | PW | 14 | -55 to 125

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SN74AHCT74MPWREP 数据手册

 浏览型号SN74AHCT74MPWREP的Datasheet PDF文件第2页浏览型号SN74AHCT74MPWREP的Datasheet PDF文件第3页浏览型号SN74AHCT74MPWREP的Datasheet PDF文件第4页浏览型号SN74AHCT74MPWREP的Datasheet PDF文件第5页浏览型号SN74AHCT74MPWREP的Datasheet PDF文件第6页浏览型号SN74AHCT74MPWREP的Datasheet PDF文件第7页 
SN74AHCT74-EP  
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH CLEAR AND PRESET  
SCLS495– JUNE 2003  
D OR PW PACKAGE  
(TOP VIEW)  
Controlled Baseline  
– One Assembly/Test Site, One Fabrication  
Site  
1CLR  
1D  
V
CC  
2CLR  
2D  
1
2
3
4
5
6
7
14  
13  
12  
11  
Extended Temperature Performance of  
–55°C to 125°C  
1CLK  
1PRE  
1Q  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
2CLK  
10 2PRE  
Enhanced Product-Change Notification  
9
8
1Q  
2Q  
2Q  
†
GND  
Qualification Pedigree  
Inputs Are TTL-Voltage Compatible  
EPIC (Enhanced-Performance Implanted  
CMOS) Process  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
†
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, Highly  
Accelerated Stress Test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life. Such qualification  
testing should not be viewed as justifying use of this component  
beyond specified performance and environmental limits.  
description/ordering information  
The SN74AHCT74 is a dual positive-edge-triggered D-type flip-flop.  
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the  
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time  
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs  
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,  
data at the D input can be changed without affecting the levels at the outputs.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
‡
PACKAGE  
T
A
SOIC – D  
Tape and reel  
Tape and reel  
SN74AHCT74MDREP  
SN74AHCT74MPWREP  
AHCT74MEP  
AHT74EP  
–55°C to 125°C  
TSSOP – PW  
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments.  
Copyright 2003, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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SN74AHCT74MPWREP 替代型号

型号 品牌 替代类型 描述 数据表
SN74AHCT74MDREP TI

完全替代

 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
5962-9686101QCA TI

完全替代

 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SNJ54AHCT74J TI

完全替代

 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

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 		DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74AHCT74PWR TI

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 		DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

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