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SN74AHCT74Q-Q1 PDF预览

SN74AHCT74Q-Q1

更新时间: 2024-09-28 12:22:47
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德州仪器 - TI 触发器
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10页 244K
描述
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

SN74AHCT74Q-Q1 数据手册

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ꢀꢁꢂ ꢃ ꢄꢅꢆ ꢇꢂ ꢃꢈ ꢉ ꢈꢊ  
ꢋꢌꢄ ꢍ ꢎꢏ ꢀꢐ ꢇ ꢐꢑꢒ ꢉꢒꢋꢓ ꢒꢉꢇ ꢔꢐ ꢓ ꢓꢒ ꢔꢒꢋ ꢋꢉꢇ ꢕꢎ ꢒ ꢖ ꢍꢐ ꢎ ꢉꢖ ꢍꢏ ꢎ  
ꢗ ꢐꢇ ꢅ ꢆꢍ ꢒꢄꢔ ꢄꢁꢋ ꢎ ꢔꢒ ꢀ ꢒꢇ  
SGDS008B − MAY 1998 − REVISED APRIL 2008  
D OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
D
Qualified for Automotive Applications  
Inputs Are TTL-Voltage Compatible  
EPIC(Enhanced-Performance Implanted  
CMOS) Process  
1CLR  
1D  
V
CC  
2CLR  
2D  
1
2
3
4
5
6
7
14  
13  
12  
11  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
1CLK  
1PRE  
1Q  
2CLK  
10 2PRE  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
9
8
1Q  
2Q  
2Q  
GND  
description  
The SN74AHCT74Q is a dual positive-edge-triggered D-type flip-flop.  
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the  
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time  
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs  
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,  
data at the D input can be changed without affecting the levels at the outputs.  
{
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
SOIC − D  
Tape and reel  
Tape and reel  
SN74AHCT74QDRQ1  
SN74AHCT74QPWRQ1  
AHCT74Q  
HB74Q  
−40°C to 125°C  
TSSOP − PW  
For the most current package and ordering information, see the Package Option Addendum at the end  
of this document, or see the TI web site at http://www.ti.com.  
Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
PRE  
L
CLR  
CLK  
X
D
X
X
X
H
L
Q
H
L
Q
L
H
L
H
X
H
§
§
H
L
L
X
H
H
H
H
H
H
L
L
H
H
H
L
X
Q
Q
0
0
§
This configuration is unstable; that is, it does not  
persist when PRE or CLR returns to its inactive  
(high) level.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments.  
ꢇꢣ  
Copyright 2008, Texas Instruments Incorporated  
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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