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SN74AHCT1G125DCKR PDF预览

SN74AHCT1G125DCKR

更新时间: 2024-11-21 17:14:59
品牌 Logo 应用领域
友台半导体 - UMW 逻辑集成电路
页数 文件大小 规格书
10页 586K
描述
逻辑集成电路

SN74AHCT1G125DCKR 数据手册

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R
UMW  
SN74AHCT1G125  
Single Bus Buffer Gate with 3-state Qutput  
Features  
General Description  
Operating Range of 4.5 V to 5.5 V  
Max tpd of 10 ns at 5 V  
The SN74AHCT1G125 device is a single bus buffer  
gate/line driver with 3-state output. The output is  
Low Power Consumption, 10 µA Max ICC  
±8mA Output Drive at 5 V  
_
E) input is high.  
disabled when the output-enable (O  
_
Inputs are TTL-Voltage Compatible  
Packages are SC70-5,SOT23-5 or small DFN6  
MSL3(SC70-5,SOT23-5DFN6(1*1.5))  
When OE is low, data is passed from the A input to  
the Y output.  
Pin Configuration  
__  
OE  
__  
OE  
1
2
3
5
4
VCC  
1
2
3
6
5
4
VCC  
NC  
Y
A
A
GND  
GND  
Y
SOT23-5/SC-70ꢀ5  
DFN6(1*1.5)  
Figure1. Top View  
www.umw-ic.com  
UTD Semiconductor Co.,Limited  
1

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