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SN74AHCT1G125DRLR PDF预览

SN74AHCT1G125DRLR

更新时间: 2024-11-04 09:16:07
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件PC
页数 文件大小 规格书
13页 574K
描述
SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT

SN74AHCT1G125DRLR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP-5针数:5
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:1.24Samacsys Confidence:3
Samacsys Status:ReleasedSamacsys PartID:609996
Samacsys Pin Count:5Samacsys Part Category:Integrated Circuit
Samacsys Package Category:SO Transistor Flat LeadSamacsys Footprint Name:DRL (R-PDS0-N5)
Samacsys Released Date:2019-11-08 07:38:50Is Samacsys:N
控制类型:ENABLE LOW计数方向:UNIDIRECTIONAL
系列:AHCT/VHCT/VTJESD-30 代码:R-PDSO-N5
JESD-609代码:e4长度:1.6 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.008 A湿度敏感等级:1
位数:1功能数量:1
端口数量:2端子数量:5
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:VSON
封装等效代码:FL6,.047,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, VERY THIN PROFILE包装方法:TR
峰值回流温度(摄氏度):260电源:5 V
最大电源电流(ICC):0.01 mAProp。Delay @ Nom-Sup:8.5 ns
传播延迟(tpd):8.5 ns认证状态:Not Qualified
座面最大高度:0.6 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:NO LEAD
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:1.2 mm
Base Number Matches:1

SN74AHCT1G125DRLR 数据手册

 浏览型号SN74AHCT1G125DRLR的Datasheet PDF文件第2页浏览型号SN74AHCT1G125DRLR的Datasheet PDF文件第3页浏览型号SN74AHCT1G125DRLR的Datasheet PDF文件第4页浏览型号SN74AHCT1G125DRLR的Datasheet PDF文件第5页浏览型号SN74AHCT1G125DRLR的Datasheet PDF文件第6页浏览型号SN74AHCT1G125DRLR的Datasheet PDF文件第7页 
ꢀꢁꢂ ꢃ ꢄꢅꢆ ꢇꢈ ꢉ ꢈꢊꢋ  
ꢀꢌ ꢁꢉ ꢍ ꢎ ꢏꢐꢀ ꢏꢐꢑ ꢑ ꢎ ꢒ ꢉ ꢄꢇꢎ  
ꢓ ꢌꢇ ꢅ ꢔ ꢕꢀꢇꢄꢇ ꢎ ꢖ ꢐꢇ ꢗꢐ ꢇ  
SCLS378L − AUGUST 1997 − REVISED JUNE 2005  
D
D
D
D
Operating Range of 4.5 V to 5.5 V  
D
D
Inputs Are TTL-Voltage Compatible  
Max t of 6 ns at 5 V  
pd  
Low Power Consumption, 10-µA Max I  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
CC  
8-mA Output Drive at 5 V  
DBV PACKAGE  
(TOP VIEW)  
DCK PACKAGE  
(TOP VIEW)  
DRL PACKAGE  
(TOP VIEW)  
1
2
3
5
OE  
A
V
Y
CC  
1
2
3
5
OE  
A
V
Y
OE  
A
V
Y
1
2
3
5
CC  
CC  
4
GND  
4
GND  
4
GND  
See mechanical drawings for dimensions.  
description/ordering information  
The SN74AHCT1G125 is a single bus buffer gate/line driver with 3-state output. The output is disabled when  
the output-enable (OE) input is high. When OE is low, true data is passed from the A input to the Y output.  
To ensure the high-impedance state during power up or power down, OE should be tied to V  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup  
CC  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
Reel of 3000  
Reel of 250  
Reel of 3000  
Reel of 250  
Reel of 4000  
SN74AHCT1G125DBVR  
SN74AHCT1G125DBVT  
SN74AHCT1G125DCKR  
SN74AHCT1G125DCKT  
SN74AHCT1G125DRLR  
SOT (SOT-23) − DBV  
B25_  
−40°C to 85°C  
SOT (SC-70) − DCK  
BM_  
BM_  
SOT (SOT-553) − DRL  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
The actual top-side marking has one additional character that designates the assembly/test site.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Y
OE  
A
H
L
L
L
H
L
H
X
Z
logic diagram (positive logic)  
1
2
OE  
A
4
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢇꢤ  
Copyright 2005, Texas Instruments Incorporated  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74AHCT1G125DRLR 替代型号

型号 品牌 替代类型 描述 数据表
SN74AHCT1G125DCKT TI

完全替代

SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
74AHCT1G125DRLRG4 TI

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SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
SN74AHCT1G125DCK TI

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SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT

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