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SN74AHC1G32_101 PDF预览

SN74AHC1G32_101

更新时间: 2024-11-04 11:49:23
品牌 Logo 应用领域
德州仪器 - TI 输入元件
页数 文件大小 规格书
13页 574K
描述
SINGLE 2-INPUT POSITIVE-OR GATE

SN74AHC1G32_101 数据手册

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ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢊ  
ꢀꢋ ꢁꢈ ꢌ ꢍ ꢊ ꢎꢋꢁ ꢏꢐꢑ ꢏꢒ ꢀꢋ ꢑ ꢋꢓꢍꢎ ꢒ ꢔ ꢈ ꢄꢑꢍ  
SCLS317N − MARCH 1996 − REVISED JUNE 2005  
D
D
D
D
Operating Range of 2 V to 5.5 V  
D
D
Schmitt Trigger Action at All Inputs Makes  
the Circuit Tolerant for Slower Input Rise  
and Fall Time  
Max t of 6.5 ns at 5 V  
pd  
Low Power Consumption, 10-µA Max I  
CC  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
8-mA Output Drive at 5 V  
DCK PACKAGE  
(TOP VIEW)  
DBV PACKAGE  
(TOP VIEW)  
DRL PACKAGE  
(TOP VIEW)  
A
B
V
Y
1
2
3
5
4
1
2
3
5
A
B
V
Y
CC  
CC  
1
2
3
5
4
A
B
V
Y
CC  
4
GND  
GND  
GND  
See mechanical drawings for dimensions.  
description/ordering information  
The SN74AHC1G32 is a single 2-input positive-OR gate. The device performs the Boolean function  
Y + A ) B or Y + A B in positive logic.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
Reel of 3000  
Reel of 250  
Reel of 3000  
Reel of 250  
Reel of 4000  
SN74AHC1G32DBVR  
SN74AHC1G32DBVT  
SN74AHC1G32DCKR  
SN74AHC1G32DCKT  
SN74AHC1G32DRLR  
SOT (SOT-23) − DBV  
A32_  
−40°C to 85°C  
SOT (SC-70) − DCK  
AG_  
AG_  
SOT (SOT-553) – DRL  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
The actual top-side marking has one additional character that designates the assembly/test site.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Y
A
B
X
H
L
H
X
L
H
H
L
logic diagram (positive logic)  
1
2
A
B
4
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢑꢡ  
Copyright 2005, Texas Instruments Incorporated  
ꢝ ꢡ ꢞ ꢝꢖ ꢗꢫ ꢙꢘ ꢜ ꢤꢤ ꢢꢜ ꢚ ꢜ ꢛ ꢡ ꢝ ꢡ ꢚ ꢞ ꢦ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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