SN74AHC123A-EP
DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATOR
www.ti.com
SCLS703A–JULY 2006–REVISED MARCH 2007
FEATURES
•
Controlled Baseline
•
•
•
Overriding Clear Terminates Output Pulse
Glitch-Free Power-Up Reset On Outputs
–
–
–
One Assembly Site
One Test Site
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
One Fabrication Site
•
ESD Protection Exceeds JESD 22
•
•
Extended Temperature Performance of –55°C
to 125°C
–
–
–
xxx
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
Enhanced Diminishing Manufacturing Sources
(DMS) Support
1000-V Charged-Device Model (C101)
•
•
•
•
Enhanced Product-Change Notification
(1)
Qualification Pedigree
D PACKAGE
(TOP VIEW)
Operating Range 2-V to 5.5-V VCC
Schmitt-Trigger Circuitry On A, B, and CLR
Inputs for Slow Input Transition Rates
1A
1B
VCC
16
15
1
2
3
4
5
6
7
8
1Rext/Cext
•
•
Edge Triggered From Active-High or
Active-Low Gated Logic Inputs
1CLR
1Q
14 1Cext
13
1Q
Retriggerable for Long Output Pulses
2Q
12 2Q
11
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
2Cext
2Rext/Cext
GND
2CLR
10
9
2B
2A
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
xxx
DESCRIPTION/ORDERING INFORMATION
The SN74AHC123A device is a dual retriggerable monostable multivibrator designed for 2-V to 5.5-V VCC
operation.
This edge-triggered multivibrator features output pulse-duration control by three methods. In the first method, the
A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In
the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.
The output pulse duration is programmed by selecting external resistance and capacitance values. The external
timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected
between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between
Rext/Cext and VCC. The output pulse duration can be reduced by taking CLR low.
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input
pulse. The A, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition
rates with jitter-free triggering at the outputs.
Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A) or
high-level-active (B) input. Pulse duration can be reduced by taking CLR low. CLR can be used to override A or
B inputs. The input/output timing diagram illustrates pulse control by retriggering the inputs and early clearing.
The variance in output pulse duration from device to device is less than ±0.5% (typ) for given external timing
components. An example of this distribution for the SN74AHC123A is shown in Figure 10. Variations in output
pulse duration versus supply voltage and temperature are shown in Figure 6.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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