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SN74ABT657ADWRE4

更新时间： 2024-11-12 21:14:55
品牌 Logo 应用领域
德州仪器 - TI 信息通信管理光电二极管逻辑集成电路
页数 文件大小 规格书
10页 188K
描述
Octal Transceivers With Parity Generators/Checkers And 3-State Outputs 24-SOIC -40 to 85

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SN74ABT657ADWRE4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP, SOP24,.4针数：24
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.54其他特性：WITH DIRECTION CONTROL
控制类型：COMMON CONTROL计数方向：BIDIRECTIONAL
系列：ABTJESD-30 代码：R-PDSO-G24
JESD-609代码：e4长度：15.4 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS TRANSCEIVER
最大I（ol）：0.064 A湿度敏感等级：1
位数：8功能数量：1
端口数量：2端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP24,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：260电源：5 V
最大电源电流（ICC）：40 mAProp。Delay @ Nom-Sup：4.6 ns
传播延迟（tpd）：4.6 ns认证状态：Not Qualified
座面最大高度：2.65 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
宽度：7.5 mmBase Number Matches：1

SN74ABT657ADWRE4 数据手册

 浏览型号SN74ABT657ADWRE4的Datasheet PDF文件第2页浏览型号SN74ABT657ADWRE4的Datasheet PDF文件第3页浏览型号SN74ABT657ADWRE4的Datasheet PDF文件第4页浏览型号SN74ABT657ADWRE4的Datasheet PDF文件第5页浏览型号SN74ABT657ADWRE4的Datasheet PDF文件第6页浏览型号SN74ABT657ADWRE4的Datasheet PDF文件第7页 
SN54ABT657A, SN74ABT657A  
OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS  
AND 3-STATE OUTPUTS  
SCBS192E – JANUARY 1991 – REVISED JUNE 1997  
SN54ABT657A . . . JT PACKAGE  
SN74ABT657A . . . DW OR NT PACKAGE  
(TOP VIEW)  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
T/R  
A1  
A2  
A3  
A4  
A5  
OE  
B1  
B2  
B3  
B4  
GND  
GND  
B5  
1
2
3
4
5
6
7
8
9
24  
23  
22  
21  
20  
19  
18  
17  
16  
Latch-Up Performance Exceeds 500 mA Per  
JEDEC Standard JESD-17  
Typical V  
(Output Ground Bounce) < 1 V  
OLP  
at V  
= 5 V, T = 25°C  
CC  
A
V
CC  
A6  
High-Impedance State During Power Up  
and Power Down  
A7  
B6  
Flow-Through Architecture Optimizes PCB  
Layout  
A8 10  
15 B7  
ODD/EVEN  
ERR  
B8  
PARITY  
11  
12  
14  
13  
High-Drive Outputs (–32-mA I , 64-mA I  
OH  
)
OL  
Package Options Include Plastic  
Small-Outline (DW) Packages, Ceramic  
Chip Carriers (FK), and Plastic (NT) and  
Ceramic (JT) DIPs  
SN54ABT657A . . . FK PACKAGE  
(TOP VIEW)  
description  
4
3
2
1
28 27 26  
25  
Th  
ABT657A transceivers have eight  
5
ODD/EVEN  
ERR  
PARITY  
NC  
A3  
A2  
A1  
NC  
T/R  
OE  
B1  
noninverting buffers with parity-generator/  
checker circuits and control signals. The  
transmit/receive (T/R) input determines the  
direction of data flow. When T/R is high, data flows  
fromtheAporttotheBport(transmitmode);when  
T/R is low, data flows from the B port to the A port  
(receive mode). When the output-enable (OE)  
input is high, both the A and B ports are in the  
high-impedance state.  
24  
23  
22  
21  
20  
19  
6
7
8
9
B8  
B7  
B6  
10  
11  
12 13 14 15 16 17 18  
Odd or even parity is selected by a logic high or  
low level on the ODD/EVEN input. PARITYcarries  
the parity-bit value; it is an output from the parity  
generator/checker in the transmit mode and an  
inputtotheparitygenerator/checkerinthereceive  
mode.  
NC – No internal connection  
In the transmit mode, after the A bus is polled to determine the number of high bits, PARITY is set to the logic  
level that maintains the parity sense selected by the level at ODD/EVEN. For example, if ODD/EVEN is low  
(even parity selected) and there are five high bits on the A bus, PARITY is set to the logic high level so that an  
even number of the nine total bits (eight A-bus bits plus parity bit) are high.  
In the receive mode, after the B bus is polled to determine the number of high bits, the error (ERR) output logic  
level indicates whether or not the data to be received exhibits the correct parity sense. For example, if  
ODD/EVEN is high (odd parity selected), PARITY is high, and there are three high bits on the B bus, ERR is  
low, indicating a parity error.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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SN74ABT657ADWRE4 替代型号

型号 品牌 替代类型 描述 数据表
SN74ABT657ADWRG4 TI

类似代替

 ABT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOIC-24

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SN74ABT657ADWRG4 TI

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 		ABT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOIC-24
SN74ABT657ANSRE4 TI

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 		ABT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24, GREEN, SOP-24
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 		ABT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24, GREEN, SOP-24
SN74ABT657ANT TI

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 		OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS
SN74ABT657ANTE4 TI

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 		ABT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDIP24, ROHS COMPLIANT, PLASTIC, DIP-24
SN74ABT657DBLE TI

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 		ABT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24
SN74ABT657DW TI

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 		暂无描述
SN74ABT657DWR TI

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 		ABT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24
SN74ABT657NT TI

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 		ABT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDIP24
SN74ABT7819 TI

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 		512 】 18 】 2 CLOCKED BIDIRECTIONAL FIRST-IN,

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