5秒后页面跳转
捷配首页

Datasheet > 暂无类别数据> SN74ABT657DW
SN74ABT657DW PDF预览

SN74ABT657DW

更新时间： 2024-11-12 12:59:31
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
9页 161K
描述
暂无描述

阅读下载

中文翻译

获取价格

SN74ABT657DW 数据手册

 浏览型号SN74ABT657DW的Datasheet PDF文件第2页浏览型号SN74ABT657DW的Datasheet PDF文件第3页浏览型号SN74ABT657DW的Datasheet PDF文件第4页浏览型号SN74ABT657DW的Datasheet PDF文件第5页浏览型号SN74ABT657DW的Datasheet PDF文件第6页浏览型号SN74ABT657DW的Datasheet PDF文件第7页 
SN54ABT657A, SN74ABT657A  
OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS  
AND 3-STATE OUTPUTS  
SCBS192E – JANUARY 1991 – REVISED JUNE 1997  
SN54ABT657A . . . JT PACKAGE  
SN74ABT657A . . . DW OR NT PACKAGE  
(TOP VIEW)  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
T/R  
A1  
A2  
A3  
A4  
A5  
OE  
B1  
B2  
B3  
B4  
GND  
GND  
B5  
1
2
3
4
5
6
7
8
9
24  
23  
22  
21  
20  
19  
18  
17  
16  
Latch-Up Performance Exceeds 500 mA Per  
JEDEC Standard JESD-17  
Typical V  
(Output Ground Bounce) < 1 V  
OLP  
at V  
= 5 V, T = 25°C  
CC  
A
V
CC  
A6  
High-Impedance State During Power Up  
and Power Down  
A7  
B6  
Flow-Through Architecture Optimizes PCB  
Layout  
A8 10  
15 B7  
ODD/EVEN  
ERR  
B8  
PARITY  
11  
12  
14  
13  
High-Drive Outputs (–32-mA I , 64-mA I  
OH  
)
OL  
Package Options Include Plastic  
Small-Outline (DW) Packages, Ceramic  
Chip Carriers (FK), and Plastic (NT) and  
Ceramic (JT) DIPs  
SN54ABT657A . . . FK PACKAGE  
(TOP VIEW)  
description  
4
3
2
1
28 27 26  
25  
Th  
ABT657A transceivers have eight  
5
ODD/EVEN  
ERR  
PARITY  
NC  
A3  
A2  
A1  
NC  
T/R  
OE  
B1  
noninverting buffers with parity-generator/  
checker circuits and control signals. The  
transmit/receive (T/R) input determines the  
direction of data flow. When T/R is high, data flows  
fromtheAporttotheBport(transmitmode);when  
T/R is low, data flows from the B port to the A port  
(receive mode). When the output-enable (OE)  
input is high, both the A and B ports are in the  
high-impedance state.  
24  
23  
22  
21  
20  
19  
6
7
8
9
B8  
B7  
B6  
10  
11  
12 13 14 15 16 17 18  
Odd or even parity is selected by a logic high or  
low level on the ODD/EVEN input. PARITYcarries  
the parity-bit value; it is an output from the parity  
generator/checker in the transmit mode and an  
inputtotheparitygenerator/checkerinthereceive  
mode.  
NC – No internal connection  
In the transmit mode, after the A bus is polled to determine the number of high bits, PARITY is set to the logic  
level that maintains the parity sense selected by the level at ODD/EVEN. For example, if ODD/EVEN is low  
(even parity selected) and there are five high bits on the A bus, PARITY is set to the logic high level so that an  
even number of the nine total bits (eight A-bus bits plus parity bit) are high.  
In the receive mode, after the B bus is polled to determine the number of high bits, the error (ERR) output logic  
level indicates whether or not the data to be received exhibits the correct parity sense. For example, if  
ODD/EVEN is high (odd parity selected), PARITY is high, and there are three high bits on the B bus, ERR is  
low, indicating a parity error.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

中文翻译

下载PDF

与SN74ABT657DW相关器件

型号 品牌 获取价格 描述 数据表
SN74ABT657DWR TI

获取价格

 		ABT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24
SN74ABT657NT TI

获取价格

 		ABT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDIP24
SN74ABT7819 TI

获取价格

 		512 】 18 】 2 CLOCKED BIDIRECTIONAL FIRST-IN,
SN74ABT7819-10PH TI

获取价格

 		512 】 18 】 2 CLOCKED BIDIRECTIONAL FIRST-IN,
SN74ABT7819-10PN TI

获取价格

 		512 】 18 】 2 CLOCKED BIDIRECTIONAL FIRST-IN,
SN74ABT7819-12PH TI

获取价格

 		512 】 18 】 2 CLOCKED BIDIRECTIONAL FIRST-IN,
SN74ABT7819-12PN TI

获取价格

 		512 】 18 】 2 CLOCKED BIDIRECTIONAL FIRST-IN,
SN74ABT7819-15PH TI

获取价格

 		512 】 18 】 2 CLOCKED BIDIRECTIONAL FIRST-IN,
SN74ABT7819-15PHR TI

获取价格

 		512X18 BI-DIRECTIONAL FIFO, 10ns, PQFP80, PLASTIC, QFP-80
SN74ABT7819-15PN TI

获取价格

 		512 】 18 】 2 CLOCKED BIDIRECTIONAL FIRST-IN,

与SN74ABT657DW相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证