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SN74ABT657DWR

更新时间： 2024-11-11 13:13:47
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
9页 161K
描述
ABT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24

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SN74ABT657DWR 技术参数

生命周期：ObsoleteReach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.54
Is Samacsys：N其他特性：WITH DIRECTION CONTROL; PARITY GENERATION A TO B; ERROR DETECTION B TO A; PROGRAMMABLE PARITY
系列：ABTJESD-30 代码：R-PDSO-G24
长度：15.4 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS TRANSCEIVER位数：8
功能数量：1端口数量：2
端子数量：24最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE最大电源电流（ICC）：30 mA
传播延迟（tpd）：4.8 ns认证状态：Not Qualified
座面最大高度：2.65 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
宽度：7.5 mmBase Number Matches：1

SN74ABT657DWR 数据手册

 浏览型号SN74ABT657DWR的Datasheet PDF文件第2页浏览型号SN74ABT657DWR的Datasheet PDF文件第3页浏览型号SN74ABT657DWR的Datasheet PDF文件第4页浏览型号SN74ABT657DWR的Datasheet PDF文件第5页浏览型号SN74ABT657DWR的Datasheet PDF文件第6页浏览型号SN74ABT657DWR的Datasheet PDF文件第7页 
SN54ABT657A, SN74ABT657A  
OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS  
AND 3-STATE OUTPUTS  
SCBS192E – JANUARY 1991 – REVISED JUNE 1997  
SN54ABT657A . . . JT PACKAGE  
SN74ABT657A . . . DW OR NT PACKAGE  
(TOP VIEW)  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
T/R  
A1  
A2  
A3  
A4  
A5  
OE  
B1  
B2  
B3  
B4  
GND  
GND  
B5  
1
2
3
4
5
6
7
8
9
24  
23  
22  
21  
20  
19  
18  
17  
16  
Latch-Up Performance Exceeds 500 mA Per  
JEDEC Standard JESD-17  
Typical V  
(Output Ground Bounce) < 1 V  
OLP  
at V  
= 5 V, T = 25°C  
CC  
A
V
CC  
A6  
High-Impedance State During Power Up  
and Power Down  
A7  
B6  
Flow-Through Architecture Optimizes PCB  
Layout  
A8 10  
15 B7  
ODD/EVEN  
ERR  
B8  
PARITY  
11  
12  
14  
13  
High-Drive Outputs (–32-mA I , 64-mA I  
OH  
)
OL  
Package Options Include Plastic  
Small-Outline (DW) Packages, Ceramic  
Chip Carriers (FK), and Plastic (NT) and  
Ceramic (JT) DIPs  
SN54ABT657A . . . FK PACKAGE  
(TOP VIEW)  
description  
4
3
2
1
28 27 26  
25  
Th  
ABT657A transceivers have eight  
5
ODD/EVEN  
ERR  
PARITY  
NC  
A3  
A2  
A1  
NC  
T/R  
OE  
B1  
noninverting buffers with parity-generator/  
checker circuits and control signals. The  
transmit/receive (T/R) input determines the  
direction of data flow. When T/R is high, data flows  
fromtheAporttotheBport(transmitmode);when  
T/R is low, data flows from the B port to the A port  
(receive mode). When the output-enable (OE)  
input is high, both the A and B ports are in the  
high-impedance state.  
24  
23  
22  
21  
20  
19  
6
7
8
9
B8  
B7  
B6  
10  
11  
12 13 14 15 16 17 18  
Odd or even parity is selected by a logic high or  
low level on the ODD/EVEN input. PARITYcarries  
the parity-bit value; it is an output from the parity  
generator/checker in the transmit mode and an  
inputtotheparitygenerator/checkerinthereceive  
mode.  
NC – No internal connection  
In the transmit mode, after the A bus is polled to determine the number of high bits, PARITY is set to the logic  
level that maintains the parity sense selected by the level at ODD/EVEN. For example, if ODD/EVEN is low  
(even parity selected) and there are five high bits on the A bus, PARITY is set to the logic high level so that an  
even number of the nine total bits (eight A-bus bits plus parity bit) are high.  
In the receive mode, after the B bus is polled to determine the number of high bits, the error (ERR) output logic  
level indicates whether or not the data to be received exhibits the correct parity sense. For example, if  
ODD/EVEN is high (odd parity selected), PARITY is high, and there are three high bits on the B bus, ERR is  
low, indicating a parity error.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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 		512X18 BI-DIRECTIONAL FIFO, 10ns, PQFP80, PLASTIC, QFP-80
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 		512X18 BI-DIRECTIONAL FIFO, 10ns, PQFP80, PLASTIC, LQFP-80

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