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SN65MLVD204DRG4 PDF预览

SN65MLVD204DRG4

更新时间： 2024-11-06 15:51:59
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管接口集成电路驱动器
页数 文件大小 规格书
31页 1050K
描述
Half-Duplex M-LVDS Transceiver 8-SOIC -40 to 85

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SN65MLVD204DRG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP, SOP8,.25针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.49
差分输出：YES驱动器位数：1
高电平输入电流最大值：0.00001 A输入特性：DIFFERENTIAL SCHMITT TRIGGER
接口集成电路类型：LINE TRANSCEIVER接口标准：EIA-899; TIA-899
JESD-30 代码：R-PDSO-G8JESD-609代码：e4
长度：4.9 mm湿度敏感等级：1
功能数量：1端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
最小输出摆幅：0.48 V最大输出低电流：0.008 A
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP8,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
最大接收延迟：6.7 ns接收器位数：1
座面最大高度：1.75 mm子类别：Line Driver or Receivers
最大压摆率：26 mA最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
最大传输延迟：4.1 ns宽度：3.9 mm
Base Number Matches：1

SN65MLVD204DRG4 数据手册

 浏览型号SN65MLVD204DRG4的Datasheet PDF文件第2页浏览型号SN65MLVD204DRG4的Datasheet PDF文件第3页浏览型号SN65MLVD204DRG4的Datasheet PDF文件第4页浏览型号SN65MLVD204DRG4的Datasheet PDF文件第5页浏览型号SN65MLVD204DRG4的Datasheet PDF文件第6页浏览型号SN65MLVD204DRG4的Datasheet PDF文件第7页 
SN65MLVD200, SN65MLVD202  
SN65MLVD204, SN65MLVD205  
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS  
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003  
D
D
D
Low-Voltage Differential 30-Ω Line Drivers  
and Receivers for Signaling Rates up to  
100 Mbps  
D
Type-2 Receivers Provide an Offset  
(100 mV) Threshold to Detect Open-Circuit  
and Idle-Bus Conditions  
†
Power Dissipation at 100 Mbps  
– Driver: 50 mW Typical  
– Receiver: 30 mW Typical  
D
D
Operates From a Single 3.3-V Supply  
Propagation Delay Times Typically 2.3 ns  
for Drivers and 5 ns for Receivers  
Meets or Exceeds Current Revision of  
M-LVDS Standard TIA/EIA–899 for  
Multipoint Data Interchange  
D
Power-Up/Down Glitch-Free Driver  
D
Driver Handles Operation Into a  
Continuous Short Circuit Without Damage  
D
D
Controlled Driver Output Voltage Transition  
Times for Improved Signal Quality  
D
D
Bus Pins High Impedance When Disabled  
or V  
≤ 1.5 V  
CC  
–1-V to 3.4-V Common-Mode Voltage Range  
Allows Data Transfer With up to 2 V of  
Ground Noise  
200-Mbps Devices Available  
(SN65MLVD201, 203, 206, and 207)  
D
Type-1 Receivers Incorporate 25 mV of  
Hysteresis  
SN65MLVD200D (Marked as MF200)  
SN65MLVD204D (Marked as MF204)  
(TOP VIEW)  
SN65MLVD202D (Marked as MLVD202)  
SN65MLVD205D (Marked as MLVD205)  
(TOP VIEW)  
R
RE  
DE  
D
V
B
A
1
2
3
4
8
7
6
5
NC  
R
V
V
A
B
Z
Y
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
CC  
CC  
CC  
RE  
GND  
DE  
D
GND  
GND  
8
NC  
NC – No internal connection  
logic diagram (positive logic)  
SN65MLVD200, SN65MLVD204  
SN65MLVD202, SN65MLVD205  
9
3
Y
DE  
5
D
DE  
RE  
10  
Z
4
D
4
3
2
RE  
R
12  
11  
A
B
6
7
2
A
B
1
R
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
†
The signaling rate of a line is the number of voltage transitions that are made per second expressed in bps (bits per second) units.  
Copyright 2001–2003, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...31

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