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SN65LVDT122PWG4 PDF预览

SN65LVDT122PWG4

更新时间: 2024-11-24 22:16:11
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德州仪器 - TI 开关
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描述
1.5-Gbps 2 x 2 LVDS CROSSPOINT SWITCH

SN65LVDT122PWG4 数据手册

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SN65LVDS122  
SN65LVDT122  
www.ti.com  
SLLS525BMAY 2002REVISED JUNE 2004  
1.5-Gbps 2 × 2 LVDS CROSSPOINT SWITCH  
FEATURES  
DESCRIPTION  
Designed for Signaling Rates (1) Up To  
1.5 Gbps  
The SN65LVDS122 and SN65LVDT122 are  
crosspoint switches that use low voltage differential  
signaling (LVDS) to achieve signaling rates as high  
as 1.5 Gbps. They are pin-compatible speed up-  
grades to the SN65LVDS22 and SN65LVDM22. The  
internal signal paths maintain differential signaling for  
high speeds and low signal skews. These devices  
have a 0-V to 4-V common-mode input range that  
accepts LVDS, LVPECL, or CML inputs. Two logic  
pins (S0 and S1) set the internal configuration be-  
tween the differential inputs and outputs. This allows  
the flexibility to perform the following configurations:  
2 x 2 crosspoint switch, 2:1 input multiplexer, 1:2  
splitter or dual repeater/translator within a single  
device. Additionally, SN65LVDT122 incorporates a  
110-termination resistor for those applications  
where board space is a premium. Although these  
devices are designed for 1.5 Gbps, some applications  
at a 2-Gbps data rate can be supported depending on  
loading and signal quality.  
Total Jitter < 65 ps  
Pin-Compatible With SN65LVDS22 and  
SN65LVDM22  
25 mV of Receiver Input Threshold Hysteresis  
Over 0-V to 4-V Common-Mode Range  
Inputs Electrically Compatible With CML,  
LVPECL and LVDS Signal Levels  
Propagation Delay Times, 900 ps Maximum  
LVDT Integrates 110-Terminating Resistor  
Offered in SOIC and TSSOP  
APPLICATIONS  
10-G (OC-192) Optical Modules  
622-MHz Central Office Clock Distribution  
Wireless Basestations  
Low Jitter Clock Repeater/Multiplexer  
Protection Switching for Serial Backplanes  
The intended application of this device is ideal for  
loopback switching for diagnostic routines, fanout  
buffering of clock/data distribution provide protection  
in fault-tolerant systems, clock multiplexing in optical  
modules, and for overall signal boosting over  
extended distances.  
(1) The signlaing rate of a line is the number of voltage  
transitions that are made per second expressed in the units  
bps (bits per second).  
The SN65LVDS122 and SN65LVDT122 are  
characterized for operation from –40°C to 85°C.  
EYE PATTERNS OF OUTPUTS  
OPERATING SIMULTANEOUSLY  
FUNCTIONAL DIAGRAM  
1DE  
1A  
1Y  
1.5 Gbps  
− 1 PRBS  
110  
23  
V
1Z  
2
OUTPUT 1  
1B  
S0  
= 3.3 V  
CC  
V
ID  
= 200 mV, V = 1.2 V  
IC  
MUX  
S1  
2A  
Vertical Scale=200 mV/div  
2Y  
2Z  
110 Ω  
OUTPUT 2  
2B  
2DE  
Integrated Termination on SN65LVDT122 Only  
Horizontal Scale= 200 ps/div  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2002–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

SN65LVDT122PWG4 替代型号

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