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SN65LVDT125 PDF预览

SN65LVDT125

更新时间: 2024-11-21 12:05:15
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德州仪器 - TI 开关
页数 文件大小 规格书
16页 250K
描述
LVDS 4X4 CROSSPOINT SWITCH

SN65LVDT125 数据手册

 浏览型号SN65LVDT125的Datasheet PDF文件第2页浏览型号SN65LVDT125的Datasheet PDF文件第3页浏览型号SN65LVDT125的Datasheet PDF文件第4页浏览型号SN65LVDT125的Datasheet PDF文件第5页浏览型号SN65LVDT125的Datasheet PDF文件第6页浏览型号SN65LVDT125的Datasheet PDF文件第7页 
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢀ ꢇꢈ ꢃ  
ꢀꢁꢂ ꢃꢄꢅ ꢆꢉ ꢇꢈ ꢃ  
www.ti.com  
SLLS555C − DECEMBER 2002 − REVISED OCTOBER 2004  
Designed to support signaling rates up to 1.5 Gbps for OC-12  
clocks (622 MHz). The 1.5-Gbps signaling rate allows use in  
HDTV systems, including SMPTE 292 video applications  
requiring signaling rates of 1.485 Gbps.  
FEATURES  
D
D
Signaling Rates >1.5 Gbps per Channel  
Supports Telecom/Datacom and HDTV Video  
Switching  
The SN65LVDS125 and SN65LVDT125 are characterized for  
operation from −40°C to 85°C.  
SN65LVDS125DBT ( Marked as LVDS125)  
SN65LVDT125DBT ( Marked as LVDT125)  
(TOP VIEW)  
D
D
Non-Blocking Architecture Allows Each  
Output to be Connected to Any Input  
Compatible With ANSI TIA/EIA-644-A LVDS  
Standard  
S10  
S11  
1A  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
1
VCC  
GND  
1Y  
1Z  
1DE  
2Y  
2
D
D
D
25 mV of Input Voltage Threshold Hysteresis  
Propagation Delay Times, 900 ps Typical  
3
1B  
4
S20  
S21  
2A  
5
Inputs Electrically Compatible With LVPECL,  
CML and LVDS Signal Levels  
6
7
2Z  
2B  
8
2DE  
GND  
VCC  
GND  
3Y  
3Z  
3DE  
4Y  
D
D
Operates From a Single 3.3-V Supply  
GND  
VCC  
GND  
3A  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
Integrated 110-Line Termination Resistors  
Available With SN65LVDT125  
3B  
S30  
S31  
4A  
4B  
S40  
S41  
APPLICATIONS  
4Z  
D
D
D
D
Clock Buffering / Clock Muxing  
Wireless Base Stations  
4DE  
GND  
VCC  
High-Speed Network Routing  
HDTV Video Switching  
Eye Pattern of Two Outputs  
Operating Simultaneously  
DESCRIPTION  
The SN65LVDS125 and SN65LVDT125 are 4x4 nonblocking  
crosspoint switches. Low-voltage differential signaling (LVDS)  
is used to achieve signaling rates of 1.5 Gbps per channel.  
Each output driver includes a 4:1 multiplexer to allow any input  
to be routed to any output. Internal signal paths are fully  
differential to achieve the high signaling speeds while  
maintaining low signal skews. The SN65LVDT125  
incorporates 110-termination resistors for those  
applications where board space is a premium.  
V
= 1.2 V  
IC  
SV S = 200 mV  
1.5 Gbps  
ID  
23  
2
−1 PRBS  
= 3.3 V  
V
CC  
200 − ps/div  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments  
semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢏꢍ ꢎ ꢆꢓ ꢌ ꢉꢐ ꢎꢁ ꢆ ꢔꢉꢔ ꢕꢖ ꢗꢘ ꢙ ꢚꢛ ꢜꢕꢘꢖ ꢕꢝ ꢞꢟ ꢙ ꢙ ꢠꢖꢜ ꢛꢝ ꢘꢗ ꢡꢟꢢ ꢣꢕꢞ ꢛꢜꢕ ꢘꢖ ꢤꢛ ꢜꢠꢥ ꢏꢙ ꢘꢤꢟ ꢞꢜꢝ  
ꢞ ꢘꢖ ꢗꢘꢙ ꢚ ꢜꢘ ꢝ ꢡꢠ ꢞ ꢕ ꢗꢕ ꢞ ꢛ ꢜꢕ ꢘꢖꢝ ꢡ ꢠꢙ ꢜꢦꢠ ꢜꢠ ꢙ ꢚꢝ ꢘꢗ ꢉꢠꢋ ꢛꢝ ꢐꢖꢝ ꢜꢙ ꢟꢚ ꢠꢖꢜ ꢝ ꢝꢜ ꢛꢖꢤ ꢛꢙ ꢤ ꢧ ꢛꢙ ꢙ ꢛ ꢖꢜꢨꢥ  
ꢏꢙ ꢘ ꢤꢟꢞ ꢜ ꢕꢘ ꢖ ꢡꢙ ꢘ ꢞ ꢠ ꢝ ꢝ ꢕꢖ ꢩ ꢤꢘ ꢠ ꢝ ꢖꢘꢜ ꢖꢠ ꢞꢠ ꢝꢝ ꢛꢙ ꢕꢣ ꢨ ꢕꢖꢞ ꢣꢟꢤ ꢠ ꢜꢠ ꢝꢜꢕ ꢖꢩ ꢘꢗ ꢛꢣ ꢣ ꢡꢛ ꢙ ꢛꢚ ꢠꢜꢠ ꢙ ꢝꢥ  
Copyright 2002−2004, Texas Instruments Incorporated  

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