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SN65LVDS94IDGG PDF预览

SN65LVDS94IDGG

更新时间： 2024-11-21 21:12:55
品牌 Logo 应用领域
德州仪器 - TI 光电二极管接口集成电路
页数 文件大小 规格书
17页 502K
描述
5 LINE TRANSCEIVER, PDSO56

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SN65LVDS94IDGG 技术参数

生命周期：Obsolete包装说明：TSSOP,
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.7
输入特性：DIFFERENTIAL接口集成电路类型：LINE TRANSCEIVER
接口标准：GENERAL PURPOSEJESD-30 代码：R-PDSO-G56
长度：14 mm功能数量：5
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH认证状态：Not Qualified
接收器位数：1座面最大高度：1.2 mm
标称供电电压：3.3 V表面贴装：YES
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
宽度：6.1 mmBase Number Matches：1

SN65LVDS94IDGG 数据手册

 浏览型号SN65LVDS94IDGG的Datasheet PDF文件第2页浏览型号SN65LVDS94IDGG的Datasheet PDF文件第3页浏览型号SN65LVDS94IDGG的Datasheet PDF文件第4页浏览型号SN65LVDS94IDGG的Datasheet PDF文件第5页浏览型号SN65LVDS94IDGG的Datasheet PDF文件第6页浏览型号SN65LVDS94IDGG的Datasheet PDF文件第7页 
SN65LVDS94  
www.ti.com  
SLLS298F–MAY 1998–REVISED JANUARY 2006  
LVDS SERDES RECEIVER  
FEATURES  
DGG PACKAGE  
(TOP VIEW)  
•
•
•
4:28 Data Channel Expansion at up to 1.904  
Gigabits per Second Throughput  
D22  
D23  
D24  
V
CC  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
Suited for Point-to-Point Subsystem  
Communication With Very Low EMI  
D21  
D20  
D19  
GND  
D18  
D17  
D16  
2
3
4 Data Channels and Clock Low-Voltage  
Differential Channels in and 28 Data and  
Clock Out Low-Voltage TTL Channels Out  
GND  
D25  
4
5
D26  
6
•
Operates From a Single 3.3-V Supply and  
250 mW (Typ)  
D27  
LVDSGND  
A0M  
7
8
•
•
•
•
5-V Tolerant SHTDN Input  
V
9
CC  
Rising Clock Edge Triggered Outputs  
Bus Pins Tolerate 4-kV HBM ESD  
A0P  
D15  
D14  
D13  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
A1M  
A1P  
Packaged in Thin Shrink Small-Outline  
Package With 20 Mil Terminal Pitch  
LVDSV  
44 GND  
CC  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
LVDSGND  
A2M  
D12  
D11  
D10  
•
•
Consumes <1 mW When Disabled  
Wide Phase-Lock Input Frequency Range  
20 MHz to 68 MHz  
A2P  
CLKINM  
CLKINP  
A3M  
V
CC  
•
•
No External Components Required for PLL  
D9  
D8  
D7  
GND  
D6  
D5  
D4  
D3  
Meets or Exceeds the Requirements of ANSI  
EIA/TIA-644 Standard  
A3P  
LVDSGND  
PLLGND  
•
•
Industrial Temperature Qualified  
TA = -40°C to 85°C  
PLLV  
Replacement for the DS90CR286  
CC  
PLLGND  
SHTDN  
CLKOUT  
D0  
V
CC  
D2  
D1  
GND  
DESCRIPTION  
The SN65LVDS94 LVDS serdes (serializer/deserializer) receiver contains four serial-in 7-bit parallel-out shift  
registers, a 7× clock synthesizer, and five low-voltage differential signaling (LVDS) line receivers in a single  
integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the  
SN65LVDS93 and SN65LVDS95, over five balanced-pair conductors and expansion to 28 bits of single-ended  
LVTTL synchronous data at a lower transfer rate.  
When receiving, the high-speed LVDS data is received and loaded into registers at the rate seven times the  
LVDS input clock (CLKIN). The data is then unloaded to a 28-bit wide LVTTL parallel bus at the CLKIN rate. A  
phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for the  
expanded data. The SN65LVDS94 presents valid data on the rising edge of the output clock (CLKOUT).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1998–2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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