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SN65LVDS95DGGREP PDF预览

SN65LVDS95DGGREP

更新时间： 2024-11-21 12:15:03
品牌 Logo 应用领域
德州仪器 - TI 线路驱动器或接收器驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
15页 364K
描述
LVDS SERDES TRANSMITTER

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中文翻译

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SN65LVDS95DGGREP 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：0.50 MM PITCH, TSSOP-48针数：48
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：0.85Is Samacsys：N
差分输出：YES驱动器位数：4
高电平输入电流最大值：0.00002 A输入特性：STANDARD
接口集成电路类型：LINE TRANSCEIVER接口标准：EIA-644; TIA-644
JESD-30 代码：R-PDSO-G48JESD-609代码：e4
长度：12.5 mm湿度敏感等级：1
功能数量：4端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：DIFFERENTIAL输出极性：COMPLEMENTARY
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP48,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
最大接收延迟：座面最大高度：1.2 mm
子类别：Line Driver or Receivers最大压摆率：110 mA
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V电源电压1-最大：3.6 V
电源电压1-分钟：3 V电源电压1-Nom：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6.1 mmBase Number Matches：1

SN65LVDS95DGGREP 数据手册

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SGLS206A − OCTOBER 2003 −REVISED SEPTEMBER 2009  
D
D
D
D
D
D
D
Controlled Baseline  
− One Assembly/Test Site, One Fabrication  
Site  
D
D
D
Inputs Meet or Exceed the Requirements of  
ANSI EIA/TIA-644 Standard  
Industrial Temperature Qualified  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
T = −40°C to 85°C  
A
Replacement for the National DS90CR215  
Enhanced Product-Change Notification  
DGG PACKAGE  
(TOP VIEW)  
†
Qualification Pedigree  
21:3 Data Channel Compression at up to  
1.36 Gigabits per Second Throughput  
D4  
D3  
1
48  
47  
46  
45  
44  
43  
Suited for Point-to-Point Subsystem  
Communication With Very Low EMI  
V
D2  
2
CC  
D5  
GND  
D1  
3
D6  
4
21 Data Channels Plus Clock in  
Low-Voltage TTL and 3 Data Channels Plus  
Clock Out Low-Voltage Differential  
GND  
D7  
D0  
5
NC  
6
D8  
7
42 LVDSGND  
41 Y0M  
D
Operates From a Single 3.3-V Supply and  
250 mW (Typ)  
V
8
CC  
D9  
9
40 Y0P  
D
5-V Tolerant Data Inputs  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
D10  
GND  
D11  
D12  
NC  
Y1M  
D
’LVDS95 Has Rising Clock Edge Triggered  
Inputs  
Y1P  
LVDSV  
CC  
D
D
Bus Pins Tolerate 6-kV HBM ESD  
LVDSGND  
Y2M  
Packaged in Thin Shrink Small-Outline  
Package With 20 Mil Terminal Pitch  
D13  
D14  
GND  
D15  
D16  
D17  
Y2P  
CLKOUTM  
CLKOUTP  
LVDSGND  
PLLGND  
D
Consumes <1 mW When Disabled  
D
Wide Phase-Lock Input Frequency Range  
20 MHz to 68 MHz  
D
No External Components Required for PLL  
PLLV  
CC  
†
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, Highly  
Accelerated Stress Test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life. Such qualification  
testing should not be viewed as justifying use of this component  
beyond specified performance and environmental limits.  
V
PLLGND  
SHTDN  
CLKIN  
D20  
CC  
D18  
D19  
GND  
description/ordering information  
The SN65LVDS95 LVDS serdes (serializer/deserializer) transmitter contains three 7-bit parallel-load serial-out  
shift registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line drivers in a single  
integrated circuit. These functions allow 21 bits of single-ended LVTTL data to be synchronously transmitted  
over 4 balanced-pair conductors for receipt by a compatible receiver, such as the SN65LVDS96.  
When transmitting, data bits D0 through D20 are each loaded into registers of the SN65LVDS95 on the rising  
edge of the input clock signal (CLKIN). The frequency of CLKIN is multiplied seven times and then used to  
serially unload the data registers in 7-bit slices. The three serial streams and a phase-locked clock (CLKOUT)  
are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...15

中文翻译

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SN65LVDS95DGGREP 替代型号

型号 品牌 替代类型 描述 数据表
SN65LVDS95DGG TI

完全替代

 LVDS SERDES TRANSMITTER
DS90C365AMT/NOPB TI

类似代替

 +3.3V 可编程 LVDS 发送器 18 位平板显示器链路 - 87.5MHz | DG
DS90CR215MTD/NOPB TI

类似代替

 DS90CR215/DS90CR216 3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 66 MHz

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