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SN65LVDS95DGG PDF预览

SN65LVDS95DGG

更新时间： 2024-11-23 22:36:59
品牌 Logo 应用领域
德州仪器 - TI 线路驱动器或接收器驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
13页 179K
描述
LVDS SERDES TRANSMITTER

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SN65LVDS95DGG 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP-48针数：48
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：0.76Is Samacsys：N
差分输出：YES驱动器位数：3
高电平输入电流最大值：0.00002 A输入特性：STANDARD
接口集成电路类型：LINE DRIVER接口标准：EIA-644; TIA-644
JESD-30 代码：R-PDSO-G48JESD-609代码：e4
长度：12.5 mm湿度敏感等级：2
功能数量：1端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：DIFFERENTIAL输出极性：COMPLEMENTARY
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP48,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
最大接收延迟：座面最大高度：1.2 mm
子类别：Line Driver or Receivers最大压摆率：110 mA
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V电源电压1-最大：3.6 V
电源电压1-分钟：3 V电源电压1-Nom：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
最大传输延迟：13.38 ns宽度：6.1 mm
Base Number Matches：1

SN65LVDS95DGG 数据手册

 浏览型号SN65LVDS95DGG的Datasheet PDF文件第2页浏览型号SN65LVDS95DGG的Datasheet PDF文件第3页浏览型号SN65LVDS95DGG的Datasheet PDF文件第4页浏览型号SN65LVDS95DGG的Datasheet PDF文件第5页浏览型号SN65LVDS95DGG的Datasheet PDF文件第6页浏览型号SN65LVDS95DGG的Datasheet PDF文件第7页 
SN65LVDS95  
LVDS SERDES TRANSMITTER  
SLLS297F – MAY 1998 – REVISED FEBRUARY 2000  
DGG PACKAGE  
(TOP VIEW)  
21:3 Data Channel Compression at up to  
1.36 Gigabits per Second Throughput  
Suited for Point-to-Point Subsystem  
Communication With Very Low EMI  
D4  
D3  
1
48  
47  
46  
45  
44  
43  
V
D2  
2
CC  
D5  
21 Data Channels Plus Clock in  
Low-Voltage TTL and 3 Data Channels Plus  
Clock Out Low-Voltage Differential  
GND  
D1  
3
D6  
4
GND  
D7  
D0  
5
Operates From a Single 3.3-V Supply and  
250 mW (Typ)  
NC  
6
D8  
7
42 LVDSGND  
41 Y0M  
5-V Tolerant Data Inputs  
V
8
CC  
D9  
9
40 Y0P  
’LVDS95 Has Rising Clock Edge Triggered  
Inputs  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
D10  
GND  
D11  
Y1M  
Y1P  
Bus Pins Tolerate 6-kV HBM ESD  
LVDSV  
CC  
Packaged in Thin Shrink Small-Outline  
Package With 20 Mil Terminal Pitch  
D12  
LVDSGND  
Y2M  
V
CC  
Consumes <1 mW When Disabled  
D13  
D14  
GND  
D15  
D16  
D17  
Y2P  
Wide Phase-Lock Input Frequency Range  
20 MHz to 65 MHz  
CLKOUTM  
CLKOUTP  
LVDSGND  
PLLGND  
No External Components Required for PLL  
Inputs Meet or Exceed the Requirements of  
ANSI EIA/TIA-644 Standard  
PLLV  
CC  
V
PLLGND  
SHTDN  
CLKIN  
D20  
CC  
Industrial Temperature Qualified  
D18  
D19  
T = –40°C to 85°C  
A
Replacement for the National DS90CR215  
GND  
description  
The SN65LVDS95 LVDS serdes (serializer/deserializer) transmitter contains three 7-bit parallel-load serial-out  
shift registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line drivers in a single  
integrated circuit. These functions allow 21 bits of single-ended LVTTL data to be synchronously transmitted  
over 4 balanced-pair conductors for receipt by a compatible receiver, such as the SN65LVDS96.  
When transmitting, data bits D0 through D20 are each loaded into registers of the SN65LVDS95 on the rising  
edge of the input clock signal (CLKIN). The frequency of CLKIN is multiplied seven times and then used to  
serially unload the data registers in 7-bit slices. The three serial streams and a phase-locked clock (CLKOUT)  
are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.  
The SN65LVDS95 requires no external components and little or no control. The data bus appears the same  
at the input to the transmitter and output of the receiver with data transmission transparent to the user(s). The  
only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock  
and shut off the LVDS output drivers for lower power consumption. A low level on this signal clears all internal  
registers to a low level.  
The SN65LVDS95 is characterized for operation over ambient air temperatures of –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

中文翻译

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SN65LVDS95DGG 替代型号

型号 品牌 替代类型 描述 数据表
SN65LVDS95DGGRQ1 TI

完全替代

 LVDS SERDES TRANSMITTER
SN65LVDS95DGGREP TI

完全替代

 LVDS SERDES TRANSMITTER
SN65LVDS95DGGR TI

完全替代

 LVDS SERDES TRANSMITTER

与SN65LVDS95DGG相关器件

型号 品牌 获取价格 描述 数据表
SN65LVDS95DGGG4 TI

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 		LVDS SERDES TRANSMITTER
SN65LVDS95DGGR TI

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 		LVDS SERDES TRANSMITTER
SN65LVDS95DGGREP TI

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 		LVDS SERDES TRANSMITTER
SN65LVDS95DGGRG4 TI

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 		LVDS SERDES TRANSMITTER
SN65LVDS95DGGRQ1 TI

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 		LVDS SERDES TRANSMITTER
SN65LVDS95-EP TI

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 		LVDS SERDES TRANSMITTER
SN65LVDS95IDGG TI

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 		暂无描述
SN65LVDS95-Q1 TI

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 		LVDS SERDES TRANSMITTER
SN65LVDS96 TI

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 		LVDS SERDES RECEIVER
SN65LVDS9637 TI

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 		HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

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