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SN65LVDS3486ID PDF预览

SN65LVDS3486ID

更新时间： 2024-01-02 00:04:58
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管接口集成电路驱动器
页数 文件大小 规格书
39页 1441K
描述
QUAD LINE TRANSCEIVER, PDSO16

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SN65LVDS3486ID 技术参数

生命周期：Obsolete包装说明：SOP,
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.67
差分输出：YES驱动器位数：1
输入特性：DIFFERENTIAL接口集成电路类型：LINE TRANSCEIVER
接口标准：EIA-644JESD-30 代码：R-PDSO-G16
长度：9.9 mm功能数量：4
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE认证状态：Not Qualified
接收器位数：1座面最大高度：1.75 mm
标称供电电压：3.3 V表面贴装：YES
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
宽度：3.9 mmBase Number Matches：1

SN65LVDS3486ID 数据手册

 浏览型号SN65LVDS3486ID的Datasheet PDF文件第2页浏览型号SN65LVDS3486ID的Datasheet PDF文件第3页浏览型号SN65LVDS3486ID的Datasheet PDF文件第4页浏览型号SN65LVDS3486ID的Datasheet PDF文件第5页浏览型号SN65LVDS3486ID的Datasheet PDF文件第6页浏览型号SN65LVDS3486ID的Datasheet PDF文件第7页 
SN55LVDS32, SN65LVDS32  
SN65LVDS3486, SN65LVDS9637  
www.ti.com  
SLLS262Q–JULY 1997–REVISED JULY 2007  
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS  
FEATURES  
SN55LVDS32 . . . J OR W  
SN65LVDS32 . . . D OR PW  
(Marked as LVDS32 or 65LVDS32)  
(TOP VIEW)  
•
Meet or Exceed the Requirements of ANSI  
TIA/EIA-644 Standard  
•
•
Operate With a Single 3.3-V Supply  
1B  
1A  
1Y  
VCC  
4B  
4A  
4Y  
G
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
Designed for Signaling Rates of up to 100  
Mbps (See Table 1)  
•
•
•
Differential Input Thresholds ±100 mV Max  
G
2Y  
Typical Propagation Delay Time of 2.1 ns  
2A  
11 3Y  
Power Dissipation 60 mW Typical Per  
Receiver at Maximum Data Rate  
10  
9
2B  
GND  
3A  
3B  
•
•
•
Bus-Terminal ESD Protection Exceeds 8 kV  
Low-Voltage TTL (LVTTL) Logic Output Levels  
SN55LVDS32FK  
(TOP VIEW)  
Pin Compatible With AM26LS32, MC3486, and  
μA9637  
•
•
Open-Circuit Fail-Safe  
3
4
2
1
20 19  
Cold Sparing for Space and High Reliability  
Applications Requiring Redundancy  
1Y  
G
4A  
4Y  
NC  
G
18  
17  
16  
15  
14  
5
6
7
NC  
2Y  
2A  
DESCRIPTION  
The SN55LVDS32, SN65LVDS32, SN65LVDS3486,  
and SN65LVDS9637 are differential line receivers  
that implement the electrical characteristics of  
low-voltage differential signaling (LVDS). This  
signaling technique lowers the output voltage levels  
of 5-V differential standard levels (such as  
EIA/TIA-422B) to reduce the power, increase the  
switching speeds, and allow operation with a 3.3-V  
supply rail. Any of the four differential receivers  
provides a valid logical output state with a ±100-mV  
differential  
common-mode  
common-mode voltage range allows 1 V of ground  
potential difference between two LVDS nodes.  
3Y  
8
9
10 11 12 13  
SN65LVDS3486D (Marked as LVDS3486)  
(TOP VIEW)  
1B  
1A  
1Y  
VCC  
4B  
4A  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
input  
voltage  
voltage  
within  
range.  
the  
The  
input  
input  
1,2EN  
2Y  
4Y  
3,4EN  
3Y  
2A  
2B  
GND  
10 3A  
3B  
The intended application of these devices and  
signaling technique is both point-to-point and  
multidrop (one driver and multiple receivers) data  
transmission over controlled impedance media of  
approximately 100 Ω. The transmission media may  
be printed-circuit board traces, backplanes, or  
cables. The ultimate rate and distance ofdata  
transfer depends on the attenuation characteristics of  
the media and the noise coupling to the environment.  
9
SN65LVDS9637D (Marked as DK637 or LVDS37)  
SN65LVDS9637DGN (Marked as L37)  
SN65LVDS9637DGK (Marked as AXF)  
(TOP VIEW)  
VCC  
1Y  
2Y  
1A  
1B  
2A  
2B  
1
2
3
4
8
7
6
5
GND  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PowerPAD is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1997–2007, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...39

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 		Quad LVDS Receiver with -4 to 5V Common-mode Range 16-SOIC -40 to 85

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