SN65LVDS108
8-PORT LVDS REPEATER
SLLS399A – NOVEMBER 1999 – REVISED MARCH 2000
DBT PACKAGE
(TOP VIEW)
One Line Receiver and Eight Line Drivers
Configured as an 8-Port LVDS Repeater
Line Receiver and Line Drivers Meet or
Exceed the Requirements of ANSI
EIA/TIA-644 Standard
GND
ANC
AY
AZ
BY
BZ
CY
CZ
DY
DZ
EY
EZ
FY
FZ
1
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
V
2
CC
GND
NC
3
Designed for Signaling Rates up to
622 Mbps
4
ENM
ENA
ENB
ENC
END
A
5
Enabling Logic Allows Individual Control of
Each Driver Output, Plus all Outputs
6
7
8
Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV and a
100Ω Load
9
10
11
12
13
14
15
16
B
Electrically Compatible With LVDS, PECL,
LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT,
SSTL, or HSTL Outputs With External
Termination Networks
ENE
ENF
ENG
ENH
NC
GY
GZ
HY
HZ
NC
NC
Propagation Delay Times < 4.7 ns
Output Skew Less Than 300 ps and
Part-to-Part Skew Less Than 1.5 ns
GND 17
18
GND 19
V
CC
Total Power Dissipation at 200 MHz
Typically Less Than 330 mW With 8
Channels Enabled
Driver Outputs or Receiver Input Equals
High Impedance When Disabled or With
V
< 1.5 V
CC
Bus-Pin ESD Protection Exceeds 12 kV
Packaged in Thin Shrink Small-Outline
Package With 20-mil Terminal Pitch
description
The SN65LVDS108 is configured as one differential line receiver connected to eight differential line drivers.
Individual output enables are provided for each output and an additional enable is provided for all outputs.
The line receivers and line drivers implement the electrical characteristics of low-voltage differential signaling
(LVDS). LVDS, as specified in EIA/TIA-644, is a data signaling technique that offers low power, low noise
emission, high noise immunity, and high switching speeds. It can be used to transmit data at speeds up to at
least 622 Mbps and over relatively long distances. (Note: The ultimate rate and distance of data transfer is
dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other
system characteristics.)
The intended application of this device, and the LVDS signaling technique, is for point-to-point or
point-to-multipoint (distributed simplex) baseband data transmission on controlled impedance media of
approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The
large number of drivers integrated into the same silicon substrate, along with the low pulse skew of balanced
signaling, provides extremely precise timing alignment of the signals being repeated from the inputs. This is
particularly advantageous for implementing system clock or data distribution trees.
The SN65LVDS108 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
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