SN65LVDS116
16-PORT LVDS REPEATER
SLLS370A – SEPTEMBER 1999 – REVISED SEPTEMBER 1999
DGG PACKAGE
(TOP VIEW)
One Receiver and Sixteen Line Drivers
Meet or Exceed the Requirements of ANSI
EIA/TIA-644 Standard
GND
A1Y
A1Z
A2Y
A2Z
A3Y
A3Z
A4Y
A4Z
B1Y
B1Z
B2Y
B2Z
B3Y
B3Z
B4Y
B4Z
C1Y
C1Z
C2Y
C2Z
C3Y
C3Z
C4Y
C4Z
D1Y
D1Z
D2Y
D2Z
D3Y
D3Z
D4Y
D4Z
1
64
63
62
61
60
59
58
57
56
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50
49
48
47
46
45
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40
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38
37
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35
34
33
Designed for Signaling Rates Up to
622 Mbps
V
2
CC
V
3
CC
Enabling Logic Allows Separate Control of
Each Bank of Four Channels or 2-Bit
Selection of Any One of the Four Banks
GND
ENA
ENA
NC
NC
NC
ENB
ENB
NC
NC
NC
4
5
6
Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV and a
100 Ω Load
7
8
9
Electrically Compatible With LVDS, PECL,
LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT,
SSTL, or HSTL Outputs With External
Termination Networks
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
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32
Propagation Delay Times <4.7 ns
GND
Output Skew is < 300 ps and Part-to-Part
Skew <1.5 ns
V
CC
V
CC
Total Power Dissipation Typically 470 mW
With All Ports Enabled and at 200 MHz
GND
A
B
NC
ENC
ENC
S0
Driver Outputs or Receiver Input is High
Impedance when Disabled or With
V
<1.5 V
CC
Bus-Pin ESD Protection Exceeds 12 kV
Packaged in Thin Shrink Small-Outline
Package With 20 Mil Terminal Pitch
S1
SM
END
END
GND
description
TheSN65LVDS116isonedifferentiallinereciever
connected to sixteen differential line drivers that
implement the electrical characteristics of
low-voltage differential signaling (LVDS). LVDS,
as specified in EIA/TIA-644, is a data signaling
technique that offers the low-power, low-noise
V
CC
V
CC
GND
coupling, and switching speeds to transmit data at speeds up to 622 Mbps and relatively long distances. (Note:
The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media,
the noise coupling to the environment, and other system characteristics.)
The intended application of this device and signaling technique is for point-to-point or multidrop baseband data
transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed
circuitboardtraces, backplanes, orcables. Thelargenumberofdriversintegratedintothesamesubstratealong
with the low pulse skew of balanced signaling, allows extremely precise timing alignment of the signals repeated
from the input. This is particularly advantageous in system clock distribution.
The SN65LVDS116 is characterised for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265