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SN54BCT646_08

更新时间： 2024-11-06 04:31:23
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德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
18页 509K
描述
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

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SN54BCT646_08 数据手册

 浏览型号SN54BCT646_08的Datasheet PDF文件第2页浏览型号SN54BCT646_08的Datasheet PDF文件第3页浏览型号SN54BCT646_08的Datasheet PDF文件第4页浏览型号SN54BCT646_08的Datasheet PDF文件第5页浏览型号SN54BCT646_08的Datasheet PDF文件第6页浏览型号SN54BCT646_08的Datasheet PDF文件第7页 
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SCBS037D − AUGUST 1989 − REVISED MAY 2004  
D
State-of-the-Art BiCMOS Design  
Significantly Reduces I  
D
Multiplexed Real-Time and Stored Data  
CCZ  
D
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
D
Bus Transceivers/Registers  
D
Independent Registers and Enables for  
A and B Buses  
SN54BCT646 . . . JT OR W PACKAGE  
SN74BCT646 . . . DW OR NT PACKAGE  
(TOP VIEW)  
SN54BCT646 . . . FK PACKAGE  
(TOP VIEW)  
CLKAB  
SAB  
DIR  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
GND  
V
CC  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
CLKBA  
SBA  
OE  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
2
3
4
3
2
1 28 27 26  
25  
A1  
A2  
A3  
NC  
A4  
A5  
A6  
OE  
B1  
B2  
NC  
B3  
B4  
B5  
5
4
24  
23  
22  
21  
20  
19  
6
5
7
6
8
7
9
8
10  
11  
9
10  
11  
12  
12 13 14 15 16 17 18  
B8  
NC − No internal connection  
description/ordering information  
These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed  
transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked  
into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1  
illustrates the four fundamental bus-management functions that can be performed with the ’BCT646 devices.  
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the  
transceiver mode, data present at the high-impedance port can be stored in either register or in both.  
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The  
direction control (DIR) determines which bus will receive data when OE is low. In the isolation mode (OE high),  
A data can be stored in one register and/or B data can be stored in the other register.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP − NT  
SOIC − DW  
Tube  
SN74BCT646NT  
SN74BCT646DW  
SN74BCT646DWR  
SNJ54BCT646JT  
SNJ54BCT646W  
SNJ54BCT646FK  
SN74BCT646NT  
Tube  
0°C to 70°C  
BCT646  
Tape and reel  
Tube  
CDIP − JT  
CFP − W  
SNJ54BCT646JT  
SNJ54BCT646W  
SNJ54BCT646FK  
−55°C to 125°C  
Tube  
LCCC − FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2004, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...18

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与SN54BCT646_08相关器件

型号 品牌 获取价格 描述 数据表
SN54BCT646DW TI

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 		BCT/FBT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, PLASTIC, SO-24
SN54BCT646DWR TI

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 		暂无描述
SN54BCT646FK TI

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 		OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54BCT646JT TI

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 		OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54BCT646NT TI

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 		BCT/FBT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CDIP24, 0.300 INCH, CERAMIC, DI
SN54BCT646W TI

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 		OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54BCT652 TI

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 		OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54BCT652_08 TI

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 		OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54BCT652FK TI

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 		OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54BCT652FK-00 TI

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 		BCT/FBT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CQCC28

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