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SN54AS181B_14

更新时间： 2024-11-25 02:58:39
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ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS

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SN54AS181B, SN74AS181A  
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS  
SDAS209B – DECEMBER 1982 – REVISED DECEMBER 1994  
SN54AS181B . . . JT OR JW PACKAGE  
SN74AS181A . . . N OR NT PACKAGE  
(TOP VIEW)  
• Full Look Ahead for High-Speed Operations  
on Long Words  
• Arithmetic Operating Modes:  
– Addition  
B0  
A0  
S3  
S2  
S1  
S0  
V
CC  
1
2
3
4
5
6
7
8
9
24  
– Subtraction  
23 A1  
22 B1  
21 A2  
20 B2  
19 A3  
18 B3  
– Shift Operand A One Position  
– Magnitude Comparison  
– Twelve Other Arithmetic Operations  
• Logic Function Modes:  
– Exclusive-OR  
C
n
– Comparator  
– AND, NAND, OR, NOR  
M
F0  
17  
16  
15  
G
C
P
n + 4  
• Package Options Include Plastic  
Small-Outline (N) Packages, Ceramic (FK)  
Chip Carriers, Standard Plastic (NT) and  
Ceramic (JT) 300-mil DIPs, and Ceramic  
(JW) 600-mil DIPs  
F1 10  
F2 11  
14 A = B  
13 F3  
GND 12  
SN54AS181B . . . FK PACKAGE  
(TOP VIEW)  
description  
The SN54AS181B and SN74AS181A arithmetic  
logic units (ALUs)/function generators have a  
complexity of 75 equivalent gates on a monolithic  
chip. These circuits perform 16 binary arithmetic  
operations on two 4-bit words as shown in  
Tables 1 and 2. These operations are selected by  
the four function-select (S0, S1, S2, and S3) lines  
and include addition, subtraction, decrement, and  
straight transfer. When performing arithmetic  
manipulations, the internal carries are enabled by  
applying a low-level voltage to the mode-control  
(M) input. A full carry look-ahead scheme is used  
to generate fast, simultaneous carry by means of  
two cascade (G and P) outputs for the four bits in  
the package.  
4
3
2
1
28 27 26  
25  
S2  
S1  
S0  
NC  
A2  
B2  
A3  
NC  
B3  
G
5
24  
23  
22  
21  
20  
19  
6
7
8
C
9
n
M
F0  
10  
11  
C
n + 4  
12 13 14 15 16 17 18  
NC – No internal connection  
If high speed is not important, a ripple-carry (C ) input and a ripple-carry (C  
) output are available. The  
n
n + 4  
ripple-carry delay is minimized so that arithmetic manipulations for small word lengths can be performed without  
external circuitry.  
The SN54AS181B and SN74AS181A accommodate active-high or active-low data if the pin designations are  
interpreted as follows:  
PIN NUMBER  
2
1
23  
A1  
A1  
22  
B1  
B1  
21  
A2  
A2  
20  
B2  
B2  
19  
A3  
A3  
18  
B3  
B3  
9
10  
F1  
F1  
11  
F2  
F2  
13  
F3  
F3  
7
16  
15  
P
17  
G
Y
Active-low data (Table 1)  
Active-high data (Table 2)  
A0  
A0  
B0  
B0  
F0  
F0  
C
C
C
n
n
n + 4  
n + 4  
C
X
Subtraction is accomplished by 1’s complement addition where the 1’s complement of the subtrahend is  
generated internally. The resultant output is A-B-1, which requires an end-around or forced carry to provide A-B.  
Copyright 1994, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

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