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SN54AS194FH-00 PDF预览

SN54AS194FH-00

更新时间： 2024-10-01 15:51:59
品牌 Logo 应用领域
德州仪器 - TI 输出元件逻辑集成电路触发器
页数 文件大小 规格书
18页 650K
描述
AS SERIES, 4-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CQCC20

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SN54AS194FH-00 技术参数

生命周期：ObsoleteReach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.84
Is Samacsys：N其他特性：HOLD MODE
计数方向：BIDIRECTIONAL系列：AS
JESD-30 代码：S-CQCC-N20长度：8.89 mm
逻辑集成电路类型：PARALLEL IN PARALLEL OUT位数：4
功能数量：1端子数量：20
最高工作温度：125 °C最低工作温度：-55 °C
输出极性：TRUE封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：QCCN封装形状：SQUARE
封装形式：CHIP CARRIER认证状态：Not Qualified
座面最大高度：2.54 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：TTL
温度等级：MILITARY端子形式：NO LEAD
端子节距：1.27 mm端子位置：QUAD
触发器类型：POSITIVE EDGE宽度：8.89 mm
Base Number Matches：1

SN54AS194FH-00 数据手册

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SDAS212A − DECEMBER 1983 − REVISED DECEMBER 1994  
SN54AS194 . . . J PACKAGE  
SN74AS194 . . . D OR N PACKAGE  
(TOP VIEW)  
• Parallel-to-Serial, Serial-to-Parallel  
Conversions  
• Left or Right Shifts  
• Parallel Synchronous Loading  
• Direct Overriding Clear  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CLR  
SR SER  
V
CC  
Q
Q
Q
Q
A
B
C
D
A
B
C
• Temporary Data-Latching Capability  
• Package Options Include Plastic  
Small-Outline Packages (D), Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
D
CLK  
S1  
S0  
SL SER  
GND  
description  
SN54AS194 . . . FK PACKAGE  
(TOP VIEW)  
These 4-bit bidirectional universal shift registers  
feature parallel outputs, right-shift and left-shift  
serial (SR SER, SL SER) inputs, operating-  
mode-control (S0, S1) inputs, and a direct  
overriding clear (CLR) line. The registers have  
four distinct modes of operation:  
3
2
1 20 19  
18  
Q
Q
A
B
4
5
6
7
8
B
C
• Inhibit clock (temporary data latch/do nothing)  
• Shift right (in the direction Q toward Q )  
17  
16  
15  
14  
NC  
NC  
C
A
D
Q
D
• Shift left (in the direction Q toward Q )  
D
A
CLK  
D
9 10 11 12 13  
• Parallel (broadside) load  
Parallel synchronous loading is accomplished by  
applying the four bits of data and taking both S0  
and S1 high. The data is loaded into the  
associated flip-flops and appears at the outputs  
after the positive transition of the clock (CLK)  
input. During loading, serial data flow is inhibited.  
NC − No internal connection  
Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low.  
Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left  
synchronously and new data is entered at the shift-left serial inputs. Clocking of the flip-flop is inhibited when  
both mode-control inputs are low.  
The SN54AS194 is characterized for operation over the full military temperature range of −55°C to 125°C. The  
SN74AS194 is characterized for operation from 0°C to 70°C.  
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Copyright 1994, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...18

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SN54AS195 TI

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 		4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
SN54AS195FH TI

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 		IC,SHIFT REGISTER,AS-TTL,LLCC,20PIN,CERAMIC
SN54AS195FK TI

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 		AS SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CQCC20, HERME
SN54AS195J TI

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 		AS SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16, 0.300
SN54AS20 TI

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 		DUAL 4-INPUT POSITIVE-NAND GATES
SN54AS20A TI

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 		DUAL 4-INPUT POSITIVE-NAND GATES
SN54AS20FH TI

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 		IC,LOGIC GATE,DUAL 4-INPUT NAND,AS-TTL,LLCC,20PIN,CERAMIC
SN54AS20FH-00 TI

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 		AS SERIES, DUAL 4-INPUT NAND GATE, CQCC20

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