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SN54ALS40AJ PDF预览

SN54ALS40AJ

更新时间: 2024-09-09 21:12:39
品牌 Logo 应用领域
德州仪器 - TI 输入元件逻辑集成电路触发器
页数 文件大小 规格书
3页 41K
描述
ALS SERIES, DUAL 4-INPUT NAND GATE, CDIP14, 0.300 INCH, CERAMIC, DIP-14

SN54ALS40AJ 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP14,.3
针数:14Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.92
其他特性:IOH = 1MA @ VOH = 2.4V; IOL = 12MA @ VOL = 0.4V系列:ALS
JESD-30 代码:R-GDIP-T14长度:19.56 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
功能数量:2输入次数:4
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):3.9 mA传播延迟(tpd):10 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:5.08 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

SN54ALS40AJ 数据手册

 浏览型号SN54ALS40AJ的Datasheet PDF文件第2页浏览型号SN54ALS40AJ的Datasheet PDF文件第3页 
SN54ALS40A, SN74ALS40A  
DUAL 4-INPUT POSITIVE-NAND BUFFERS  
SDAS197 – D2661, APRIL 1984 – REVISED MAY 1986  
SN54ALS40A . . . J PACKAGE  
SN74ALS40A . . . D OR N PACKAGE  
Package Options include Plastic Small  
Outline Packages, Ceramic Chip Carriers,  
and Standard Plastic and Ceramic 300-mil  
DIPs  
(TOP VIEW)  
1A  
1B  
NC  
1C  
1D  
1Y  
V
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
CC  
Dependable Texas Instruments Quality and  
2D  
2C  
NC  
2B  
2A  
2Y  
Reliability  
description  
These devices contain two independent 4-input  
NAND buffer gates. They perform the Boolean  
functions Y = ABCD or Y = A + B + C+ D in  
positive logic.  
GND  
8
SN54ALS40A . . . FK PACKAGE  
(TOP VIEW)  
The SN54ALS40A is characterized for operation  
over the full military temperature range of – 55°C  
to 125°C. The SN74ALS40A is characterized for  
operation from 0°C to 70°C.  
3
2
1
20 19  
18  
FUNCTION TABLE  
(each gate)  
2C  
2C  
NC  
NC  
2B  
NC  
NC  
1C  
NC  
1D  
4
5
6
7
8
17  
16  
15  
14  
INPUTS  
OUTPUT  
A
H
L
B
H
X
L
C
H
X
X
L
D
H
X
X
X
L
Y
L
9 10 11 12 13  
H
H
H
H
X
X
X
X
X
X
NCNo internal connection  
logic symbol  
logic diagram (positive logic)  
1
&
1A  
1A  
2
6
1B  
1Y  
1B  
1C  
1Y  
2Y  
4
1C  
5
1D  
1D  
9
2A  
2A  
8
2Y  
10  
12  
13  
2B  
2C  
2D  
2B  
2C  
2D  
This symbol is in accordance with ANSI/IEEE Std 91-1984  
and IEC Publication 617-12.  
Pin numbers shown are for D, J, and N packages.  
Copyright 1986, Texas Instruments Incorporated  
5BASIC  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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