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SN54ALS1010AFKR PDF预览

SN54ALS1010AFKR

更新时间: 2024-11-06 20:37:07
品牌 Logo 应用领域
德州仪器 - TI 输入元件逻辑集成电路
页数 文件大小 规格书
3页 54K
描述
ALS SERIES, TRIPLE 3-INPUT NAND GATE, CQCC20, CERAMIC, LCC-20

SN54ALS1010AFKR 技术参数

生命周期:Obsolete零件包装代码:QLCC
包装说明:QCCN,针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.72其他特性:IOH = 1MA @ VOH = 2.4V; IOL = 12MA @ VOL = 0.4V
系列:ALSJESD-30 代码:S-CQCC-N20
长度:8.89 mm负载电容(CL):50 pF
逻辑集成电路类型:NAND GATE功能数量:3
输入次数:3端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QCCN
封装形状:SQUARE封装形式:CHIP CARRIER
最大电源电流(ICC):5.8 mA传播延迟(tpd):12 ns
认证状态:Not Qualified座面最大高度:2.03 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:MILITARY
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD宽度:8.89 mm
Base Number Matches:1

SN54ALS1010AFKR 数据手册

 浏览型号SN54ALS1010AFKR的Datasheet PDF文件第2页浏览型号SN54ALS1010AFKR的Datasheet PDF文件第3页 
ꢀꢁ ꢂꢃ ꢄꢅ ꢀ ꢆꢇ ꢆ ꢇ ꢄꢈ ꢉꢀ ꢁꢊ ꢃ ꢄꢅ ꢀꢆ ꢇꢆ ꢇꢄ  
ꢋ ꢌꢍꢎ ꢅꢏ ꢉꢐ ꢑꢍ ꢁꢎꢒꢋ ꢉ ꢎꢓ ꢀꢍꢋ ꢍ ꢔꢏꢑꢁ ꢄꢁꢕꢉꢖ ꢒꢗ ꢗꢏ ꢌ ꢀ  
SDAS075A − D2661, APRIL 1982 − REVISED MAY 1986  
Buffer Version of ’ALS10A  
SN54ALS1010A . . . J PACKAGE  
SN74ALS1010A . . . D OR N PACKAGE  
Package Options include Plastic Small  
Outline DIPs and Ceramic Chip Carriers in  
Addition to the Standard 300-mil Plastic  
and Ceramic DIPs.  
(TOP VIEW)  
1A  
1B  
2A  
2B  
2C  
V
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
CC  
1C  
1Y  
3C  
3B  
3A  
3Y  
Dependable Texas Instruments Quality and  
Reliability  
description  
2Y  
GND  
8
These devices contain three independent 3-input  
NAND buffers. They perform the Boolean  
functions Y = ABC or Y = A+B+C in positive logic.  
SN54ALS1010A . . . FK PACKAGE  
(TOP VIEW)  
The SN54ALS1010A is characterized for opera-  
tion over the full military temperature range of  
−55°C to 125°C. The SN74ALS1010A is  
characterized for operation from 0°C to 70°C.  
3
2
1
20 19  
18  
1Y  
NC  
3C  
NC  
3B  
2A  
NC  
2B  
4
5
6
7
8
FUNCTION TABLE  
(each gate)  
17  
16  
15  
14  
INPUTS  
B
OUTPUT  
NC  
2C  
A
H
L
C
H
X
X
L
Y
L
9 10 11 12 13  
H
X
L
H
H
H
X
X
X
NC − No internal connection  
logic symbol †  
logic diagram (positive logic)  
1
1A  
1B  
1C  
1A  
&
1Y  
2
12  
1Y  
1B  
13  
1C  
3
2A  
2B  
2C  
2A  
2Y  
3Y  
6
4
2Y  
2B  
5
2C  
9
3A  
3B  
3C  
3A  
10  
8
3B  
3Y  
11  
3C  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
Pin numbers shown are for D, J, and N packages.  
ꢋꢥ  
Copyright 1986, Texas Instruments Incorporated  
ꢡ ꢥ ꢢ ꢡꢚ ꢛꢯ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢪ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001  

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