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SN54ALS1005J-00 PDF预览

SN54ALS1005J-00

更新时间: 2024-11-04 21:10:11
品牌 Logo 应用领域
德州仪器 - TI 输入元件逻辑集成电路
页数 文件大小 规格书
14页 741K
描述
ALS SERIES, HEX 1-INPUT INVERT GATE, CDIP14

SN54ALS1005J-00 技术参数

生命周期:Obsolete包装说明:DIP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.56系列:ALS
JESD-30 代码:R-GDIP-T14长度:19.56 mm
负载电容(CL):50 pF逻辑集成电路类型:INVERTER
功能数量:6输入次数:1
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C输出特性:OPEN-COLLECTOR
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
最大电源电流(ICC):12 mA传播延迟(tpd):12 ns
认证状态:Not Qualified座面最大高度:5.08 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

SN54ALS1005J-00 数据手册

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ꢋꢌ ꢍꢉꢎ ꢁꢏꢌ ꢐꢑ ꢎꢁꢒ ꢉ ꢓꢔ ꢕꢕ ꢌ ꢐ  
SDAS240A − APRIL 1982 − REVISED JANUARY 1995  
SN54ALS1005 . . . J PACKAGE  
SN74ALS1005 . . . D OR N PACKAGE  
(TOP VIEW)  
Buffer Versions of ALS05A  
Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
1A  
1Y  
2A  
2Y  
3A  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
6A  
6Y  
5A  
5Y  
4A  
4Y  
description  
These devices contain six independent inverting  
buffers. They perform the Boolean function Y = A.  
The open-collector outputs require pullup  
resistors to perform correctly. These outputs can  
be connected to other open-collector outputs to  
implement active-low wired-OR or active-high  
wired-AND functions. Open-collector devices are  
3Y  
GND  
8
SN54ALS1005 . . . FK PACKAGE  
(TOP VIEW)  
often used to generate higher V  
levels.  
OH  
The SN54ALS1005 is characterized for operation  
over the full military temperature range of 55°C  
to 125°C. The SN74ALS1005 is characterized for  
operation from 0°C to 70°C.  
3
2
1
20 19  
18  
2A  
NC  
2Y  
4
5
6
7
8
6Y  
NC  
5A  
NC  
5Y  
17  
16  
15  
14  
NC  
3A  
FUNCTION TABLE  
(each inverter)  
9 10 11 12 13  
INPUT  
A
OUTPUT  
Y
H
L
L
NC − No internal connection  
H
logic symbol  
logic diagram (positive logic)  
1
1A  
3
2
4
1
2
4
1Y  
2Y  
3Y  
4Y  
5Y  
6Y  
1A  
1Y  
2A  
5
6
3
3A  
9
2A  
2Y  
3Y  
4Y  
5Y  
6Y  
8
4A  
11  
10  
12  
5
6
5A  
13  
3A  
6A  
9
8
4A  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
Pin numbers shown are for the D, J, and N packages.  
11  
10  
12  
5A  
13  
6A  
ꢑꢧ  
Copyright 1995, Texas Instruments Incorporated  
ꢣ ꢧ ꢤ ꢣꢜ ꢝꢱ ꢟꢞ ꢢ ꢪꢪ ꢨꢢ ꢠ ꢢ ꢡ ꢧ ꢣ ꢧ ꢠ ꢤ ꢬ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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