Datasheet > SN54ACT3632

SN54ACT3632

更新时间： 2024-11-14 22:59:11

品牌	Logo	应用领域
德州仪器 - TI		存储
页数	文件大小	规格书
25页	384K
描述
512 】 36 】 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

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SN54ACT3632 数据手册

SN54ACT3632

512 × 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998

Free-Running CLKA and CLKB Can Be

Released as DESC SMD (Standard

Asynchronous or Coincident

Microcircuit Drawing) 5962-9562801QYA

Two Independent 512 × 36 Clocked FIFOs

Buffering Data in Opposite Directions

IRB, ORB, AEB, and AFB Flags

Synchronized by CLKB

Mailbox-Bypass Register for Each FIFO

Low-Power 0.8-µm Advanced CMOS

Technology

Programmable Almost-Full and

Almost-Empty Flags

Supports Clock Frequencies up to 50 MHz

Fast Access Times of 13 ns

Microprocessor Interface Control Logic

IRA, ORA, AEA, and AFA Flags

Synchronized by CLKA

Packaged in 132-Pin Ceramic Quad Flat

Package

description

The SN54ACT3632 is a high-speed, low-power CMOS clocked bidirectional FIFO memory. It supports clock

frequencies up to 50 MHz and has read access times as fast as 11 ns. Two independent 512 × 36 dual-port

SRAM FIFOs on the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full

conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of

words is stored in memory. Communication between each port can bypass the FIFOs via two 36-bit mailbox

registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more devices can

be used in parallel to create wider data paths.

The SN54ACT3632 is a clocked FIFO, which means each port employs a synchronous interface. All data

transfers through a port are gated to the low-to-high transition of a port clock by enable signals. The clocks for

each port are independent of one another and can be asynchronous or coincident. The enables for each port

are arranged to provide a simple bidirectional interface between microprocessors and/or buses with

synchronous control.

The input-ready (IRA, IRB) flag and almost-full (AFA, AFB) flag of a FIFO are two-stage synchronized to the

port clock that writes data to its array. The output-ready (ORA, ORB) flag and almost-empty (AEA, AEB) flag

of a FIFO are two-stage synchronized to the port clock that reads data from its array. Offset values for the

almost-full and almost-empty flags of both FIFOs can be programmed from port A.

The SN54ACT3632 is characterized for operation over the full military temperature range of –55°C to 125°C.

For more information on this device family, see the following application reports:

FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control

(literature number SCAA007)

Interfacing TI Clocked FIFOs With TI Floating-Point Digital Signal Processors (literature number SCAA005)

Metastability Performance of Clocked FIFOs (literature number SCZA004)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...25

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SN54ACT3632 替代型号

型号	品牌	替代类型	描述	数据表
SN74ACT3632	TI	功能相似	512 】 36 】 2 CLOCKED BIDIRECTIONAL FIRST-IN,

与SN54ACT3632相关器件

型号	品牌	获取价格	描述	数据表
SN54ACT3632HFP	TI	获取价格	512 】 36 】 2 CLOCKED BIDIRECTIONAL FIRST-IN,
SN54ACT3632HFPR	TI	获取价格	512X36 BI-DIRECTIONAL FIFO, 15ns, CQFP132, CERAMIC, QFP-132
SN54ACT3641	TI	获取价格	1024 】 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SN54ACT3641HFP	TI	获取价格	1024 】 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SN54ACT3641PCB	TI	获取价格	1024 】 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SN54ACT3641PCBR	TI	获取价格	1KX36 OTHER FIFO, 15ns, PQFP120
SN54ACT373	TI	获取价格	OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SN54ACT373_02	TI	获取价格	OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SN54ACT373_07	TI	获取价格	OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SN54ACT373FK	TI	获取价格	OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

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