Datasheet > 存储 > FIFO> SN54ACT3641HFP

SN54ACT3641HFP

更新时间： 2024-11-14 22:09:51

品牌	Logo	应用领域
德州仪器 - TI		存储内存集成电路先进先出芯片时钟
页数	文件大小	规格书
26页	378K
描述
1024 】 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

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SN54ACT3641HFP 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	QFF, QFL132,.95SQ,25
针数：	132	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.32.00.71
风险等级：	5.92	Is Samacsys：	N
最长访问时间：	15 ns	最大时钟频率 (fCLK)：	50 MHz
周期时间：	20 ns	JESD-30 代码：	S-GQFP-F132
长度：	24.13 mm	内存密度：	36864 bit
内存集成电路类型：	BI-DIRECTIONAL FIFO	内存宽度：	36
功能数量：	1	端子数量：	132
字数：	1024 words	字数代码：	1000
工作模式：	SYNCHRONOUS	最高工作温度：	125 °C
最低工作温度：	-55 °C	组织：	1KX36
可输出：	YES	封装主体材料：	CERAMIC, GLASS-SEALED
封装代码：	QFF	封装等效代码：	QFL132,.95SQ,25
封装形状：	SQUARE	封装形式：	FLATPACK
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V	认证状态：	Not Qualified
座面最大高度：	3.81 mm	子类别：	FIFOs
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	MILITARY
端子形式：	FLAT	端子节距：	0.635 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	24.13 mm	Base Number Matches：	1

SN54ACT3641HFP 数据手册

SN54ACT3641

1024 × 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SGBS309A – AUGUST 1995 – REVISED APRIL 1998

Free-Running CLKA and CLKB Can Be

Asynchronous or Coincident

Output-Ready and Almost-Empty Flags

Synchronized by CLKB

Clocked FIFO Buffering Data From Port A

to Port B

Low-Power 0.8 µm Advanced CMOS

Technology

Memory Size: 1024 × 36

Supports Clock Frequencies up to 50 MHz

Fast Access Times of 15 ns

Synchronous Read-Retransmit Capability

Mailbox Register in Each Direction

Released as DSCC SMD (Standard

Microcircuit Drawing) 5962-9560801QYA

and 5962-9560801NXD

Programmable Almost-Full and

Almost-Empty Flags

Package Options include 132-Pin Ceramic

Quad Flat (HFP) and 120-Pin Plastic Quad

Flat (PCB) Packages

Microprocessor Interface Control Logic

Input-Ready and Almost-Full Flags

Synchronized by CLKA

description

The SN54ACT3641 is a high-speed, low-power, CMOS clocked FIFO memory. It supports clock frequencies

up to 50 MHz and has read access times as fast as 15 ns. The 1024 × 36 dual-port SRAM FIFO buffers data

from port A to port B. The FIFO memory has retransmit capability, which allows previously read data to be

accessed again. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost

full and almost empty) to indicate when a selected number of words is stored in memory. Communication

between each port can take place with two 36-bit mailbox registers. Each mailbox register has a flag to signal

when new mail has been stored. Two or more devices can be used in parallel to create wider datapaths.

Expansion is also possible in word depth.

The SN54ACT3641 is a clocked FIFO, which means each port employs a synchronous interface. All data

transfersthroughaportaregatedtothelow-to-hightransitionofacontinuous(free-running)portclockbyenable

signals. The continuous clocks for each port are independent of one another and can be asynchronous or

coincident. The enables for each port are arranged to provide a simple interface between microprocessors

and/or buses with synchronous control.

The input-ready (IR) flag and almost-full (AF) flag of the FIFO are two-stage synchronized to CLKA. The

output-ready (OR) flag and almost-empty (AE) flag of the FIFO are two-stage synchronized to CLKB. Offset

values for the AF and AE flags of the FIFO can be programmed from port A or through a serial input.

The SN54ACT3641 is characterized for operation over the full military temperature range of – 55°C to 125°C.

For more information on this device family, see the following application reports:

•

FIFO Patented Synchronous Retransmit: Programmable DSP-Interface Application for FIR Filtering

(literature number SCAA009)

FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control

(literature number SCAA007)

Metastability Performance of Clocked FIFOs (literature number SCZA004)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...26

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与SN54ACT3641HFP相关器件

型号	品牌	获取价格	描述	数据表
SN54ACT3641PCB	TI	获取价格	1024 】 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SN54ACT3641PCBR	TI	获取价格	1KX36 OTHER FIFO, 15ns, PQFP120
SN54ACT373	TI	获取价格	OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SN54ACT373_02	TI	获取价格	OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SN54ACT373_07	TI	获取价格	OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SN54ACT373FK	TI	获取价格	OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SN54ACT373J	TI	获取价格	OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SN54ACT373-SP	TI	获取价格	具有三态输出的八路 D 类透明锁存器
SN54ACT373W	TI	获取价格	OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SN54ACT374	TI	获取价格	OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS

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