Datasheet > SN54165_15

SN54165_15

更新时间： 2024-09-09 02:58:47

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
13页	199K
描述
PARALLEL-LOAD 8-BIT SHIFT REGISTERS

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

SN54165_15 数据手册

SN54165, SN54LS165A, SN74165, SN74LS165A

PARALLEL-LOAD 8-BIT SHIFT REGISTERS

The SN54165 and SN74165 devices

are obsolete and are no longer supplied.

SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002

SN54165, SN54LS165A . . . J OR W PACKAGE

SN74165 . . . N PACKAGE

Complementary Outputs

Direct Overriding Load (Data) Inputs

Gated Clock Inputs

SN74LS165A . . . D, N, OR NS PACKAGE

(TOP VIEW)

Parallel-to-Serial Data Conversion

SH/LD

CLK

CLK INH

TYPICAL MAXIMUM

CLOCK FREQUENCY POWER DISSIPATION

TYPICAL

TYPE

’165

26 MHz

35 MHz

210 mW

90 mW

’LS165A

description

SER

GND

The ’165 and ’LS165A are 8-bit serial shift

registers that shift the data in the direction of Q

toward Q when clocked. Parallel-in access to

SN54LS165A . . . FK PACKAGE

(TOP VIEW)

each stage is made available by eight individual,

direct data inputs that are enabled by a low level

at the shift/load (SH/LD) input. These registers

also feature gated clock (CLK) inputs and

complementary outputs from the eighth bit. All

inputs

are

diode-clamped

to minimize

20 19

transmission-line effects, thereby simplifying

system design.

Clocking is accomplished through a two-input

positive-NOR gate, permitting one input to be

used as a clock-inhibit function. Holding either of

the clock inputs high inhibits clocking, and holding

either clock input low with SH/LD high enables the

other clock input. Clock inhibit (CLK INH) should

be changed to the high level only while CLK is

high. Parallel loading is inhibited as long asSH/LD

is high. Data at the parallel inputs are loaded

directly into the register while SH/LD is low,

independently of the levels of CLK, CLK INH, or

serial (SER) inputs.

9 10 11 12 13

NC – No internal connection

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...13

中文翻译

下载PDF

与SN54165_15相关器件

型号	品牌	获取价格	描述	数据表
SN54165J	TI	获取价格	PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SN54165J-00	TI	获取价格	TTL/H/L SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, C
SN54165W	TI	获取价格	PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SN54165W-10	TI	获取价格	TTL/H/L SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, C
SN54166	TI	获取价格	PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SN54166_15	TI	获取价格	PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SN54166J	TI	获取价格	PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SN54166J-00	TI	获取价格	TTL/H/L SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16
SN54166W	TI	获取价格	PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SN54167	TI	获取价格	SYNCHRONOUS DECADE RATE MULTIPLIERS

与SN54165_15相关文章

SL74HC10N：高性能三输入与非门解析
2024-09-03

56
AIC1781A 电池充电控制器深度解析
2024-09-03

48
Pickering新高压舌簧继电器亮相汽车测试博览会
2024-08-26

81
采用MCU+MPU双处理器架构实现的创新应用设计探索
2024-08-23

92

产品中心

服务支持

精选活动

关于我们

帮助中心

SN54165_15

SN54165_15 数据手册

与SN54165_15相关器件

与SN54165_15相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

SN54165_15

SN54165_15 数据手册

与SN54165_15相关器件

与SN54165_15相关文章

您还可以找

您在本页遇到什么问题？