Datasheet > SN100KT5574DW

SN100KT5574DW

更新时间： 2024-10-16 02:58:47

品牌	Logo	应用领域
德州仪器 - TI		光电二极管输出元件接口集成电路锁存器
页数	文件大小	规格书
8页	71K
描述
OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND 3-STATE OUTPUTS

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SN100KT5574DW 数据手册

SN100KT5574

OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE

EDGE-TRIGGERED FLIP-FLOPS AND 3-STATE OUTPUTS

SDZS009 – D3418, JANUARY 1990

DW OR NT PACKAGE

(TOP VIEW)

• 100K Compatible

• ECL Clock and TTL Control Inputs

• Flow-Through Architecture Optimizes PCB

Layout

• Center Pin V , V , and GND

CC EE

Configurations Minimize High-Speed

Switching Noise

OE(TTL)

GND

• Package Options Include “Small Outline”

GND

CLK(ECL)

Packages and Standard Plastic DIPs

description

This octal ECL-to-TTL translator is designed to

provide efficient translation between a 100K ECL

signal environment and a TTL signal environment.

This device is designed specifically to improve the performance and density of ECL-to-TTL CPU/bus-oriented

functions such as memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.

The eight flip-flops of the SN100KT5574 are edge-triggered D-type flip-flops. On the positive transition of the

clock, the Q outputs are set to the logic levels that were set up at the D inputs.

A buffered output-enable input (OE) can be used to place the eight outputs in either a normal logic state (high

or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive

the bus lines significantly. The high-impedance third state and increased drive provide the capability to drive

bus lines without need for interface or pullup components.

The output-enable input OE does not affect the internal operations of the flip-flops. Old data can be retained

or new data can be entered while the outputs are off.

The SN100KT5574 is characterized for operation from 0°C to 85°C.

FUNCTION TABLE

OUTPUT

INPUTS

(TTL)

CLK

↑

PRODUCTION DATA information is current as of publication date. Products

conform to specifications per the terms of Texas Instruments standard

warranty. Production processing does not necessarily include testing of all

parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7 8

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与SN100KT5574DW相关器件

型号	品牌	获取价格	描述	数据表
SN100KT5574DWR	TI	获取价格	暂无描述
SN100KT5574NT	TI	获取价格	Octal ECL-to-TTL Translator With D-type Edge-Triggered Flip-Flops And 3-State OU 24-PDIP 0
SN100KT5576NT	TI	获取价格	OCTAL ECL TO TTL TRANSLATOR, INVERTED OUTPUT, PDIP24
SN100KT5578	TI	获取价格	OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE
SN100KT5578DW	TI	获取价格	Octal TTL-to-ECL Translator With D-type Edge-Triggered Flip-Flops And Output ENA 24-SOIC 0
SN100KT5578NT	TI	获取价格	Octal TTL-to-ECL Translator With D-type Edge-Triggered Flip-Flops And Output ENA 24-PDIP 0
SN100M0010A5F51012	YAGEO	获取价格	Aluminum Electrolytic Capacitor, Non-polarized, Aluminum (wet), 100V, 20% +Tol, 20% -Tol,
SN100M0010APF-0811	YAGEO	获取价格	Aluminum Electrolytic Capacitor, Non-polarized, Aluminum (wet), 100V, 20% +Tol, 20% -Tol,
SN100M0010B3F50811	YAGEO	获取价格	Aluminum Electrolytic Capacitor, Non-polarized, Aluminum (wet), 100V, 20% +Tol, 20% -Tol,
SN100M0010L5SW1012	YAGEO	获取价格	Aluminum Electrolytic Capacitor, Non-polarized, Aluminum, 100V, 20% +Tol, 20% -Tol, 10uF,

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